NDLI: Low-latency power-efficient adaptive router design for network-on-chip

Content Provider	IEEE Xplore Digital Library
Author	Nasirian, Nasim Bayoumi, Magdy
Copyright Year	2015
Description	Author affiliation: The Center for Advanced Computer Studies, University of Louisiana, Lafayette Lafayette, Louisiana 70504 (Nasirian, Nasim) \|\| The Center for Advanced Computer Studies, University of Louisiana, Lafayette, Lafayette, Louisiana 70504 (Bayoumi, Magdy)
Abstract	Network-on-chip (NOC) technology has offered an efficient solution for scalability problem. Following the advent of the NOC technology, decreasing the static power consumption has been at the focus of research and development. Since the routers are the most important and main power-consuming modules of NOC, most of the contributions are related to improvement in router micro-architecture design [1], [2]. Power-gating is currently an effective solution in this area but it causes overhead in terms of delays and in some cases it deteriorates the performance. In this paper, a power efficient design for the network-on-chip (NOC) routers using adaptive routing has been proposed. The Proposed scheme is directing the traffic in a power-gated network with respect to the routers status. In this way, we avoid to turn on the routers, that are in sleep state by alternating the paths. Our simulation has shown that we can achieve near 80% reduction in static power consumption compared to non-power-gated design and we improved the average delay by 35% in comparison with conventional power-gated design.
Starting Page	287
Ending Page	291
File Size	449325
Page Count	5
File Format	PDF
ISSN	21641706
e-ISBN	9781467390941
DOI	10.1109/SOCC.2015.7406965
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-08
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Ports (Computers) Routing Delays Power demand Computer architecture Switches Queueing analysis System-on-Chip (SOC) Network-on-Chip (NOC) wormhole switching Routing Computation (RC)
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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