NDLI: Area and power efficient network on chip router architecture

Content Provider	IEEE Xplore Digital Library
Author	Sahu, S. Kittur, H.M.
Copyright Year	2013
Description	Author affiliation: VLSI Div., VIT Univ., Vellore, India (Sahu, S.; Kittur, H.M.)
Abstract	In System on Chip, buses and point to point links are used as a communication infrastructure between one IP to another, but these cannot provide efficient interconnect from performance point of view. So NoC architecture was proposed to provide communication in multiprocessor SoC and overcome the limitations. This paper has implemented a 5-port 32-bit and 64-bit router architecture using wormhole routing technique for 2D-mesh network by using simple deterministic algorithm, flow control and decoding mechanism. In this router, 2 types of crossbar are used named as multiplexer and tri-state buffer matrix for efficient design. Comparisons of area and power are done for these router designs using ASIC tool flow in Cadence using TSMC 90nm and 180nm process technologies. Simulation results are performed in Cadence NC simulator. It is demonstrated that multiplexer router design is more efficient than a matrix router design as area and power increases for matrix design while using same port-width.
Sponsorship	IEEE
Starting Page	855
Ending Page	859
File Size	854045
Page Count	5
File Format	PDF
ISBN	9781467357593
e-ISBN	9781467357586
DOI	10.1109/CICT.2013.6558214
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-11
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing Mesh network Network on chip (NoC) Conferences Ports (Computers) System on Chip (SoC) Switches Computer architecture Routing Wormhole routing System-on-chip Deterministic Algorithm
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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