NDLI: Test generation for (sequential) multi-valued logic networks based on genetic algorithm

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Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)

Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)

Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)

Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)

Table of contents

Advanced circuit technology to realize post giga-bit DRAM

Development of InGaAs-based multiple-junction surface tunnel transistors for multiple-valued logic circuits

Ultrafast ternary quantizer using resonant tunneling devices

A Josephson ternary memory circuit

A note on realizing multiple-valued logic functions using Akers' cells-cell sizes and path lengths

Minimization of exclusive sums of multi-valued complex terms for logic cell arrays

Minimal test set generation for fault diagnosis in R-valued PLAs

Design of multiple-output networks using time domain multiplexing and shared multi-terminal multiple-valued decision diagrams

Implementing a multiple-valued decision diagram package

Ternary decision diagrams with inverted edges and cofactoring-an application to discrete neural networks synthesis

The MacLaurin's and Taylor's series expansions of the symbolic multiple valued logic functions

A characterization of r-valued functions monotonic in an order based on regularity

Some results on the decision for Sheffer functions in partial K-valued logic. II

On the properties of multiple-valued functions that are symmetric in both variable values and labels

Evolutionary methods in the design of quaternary digital circuits

Look-up table FPGA synthesis from minimized multi-valued pseudo Kronecker expressions

Multiple-valued logics for theorem-proving in first order logic with equality

Compact propositional Godel logics

Many-valued and annotated modal logics

The FPGA challenge

Application of neuron-MOS to current-mode multi-valued logic circuits

Asynchronous multiple-valued VLSI system based on dual-rail current-mode differential logic

Set-valued logic circuits for next generation VLSI architectures

Wave-parallel computing systems using multiple-valued pseudo-orthogonal sequences

Image segmentation based on Kleene algebra

Learning with permutably homogeneous multiple-valued multiple-threshold perceptrons

An error reducing approach to machine learning using multi-valued functional decomposition

Multi-valued functional decomposition as a machine learning method

Fast multi-polarity complex Hadamard transform for logic functions

Reed-Muller-Fourier versus Galois field representations of four-valued logic functions

Constructing an MVL patterned after Boolean logic using a practical approach

A synthesis method of the approximate reasoning engine by means of genetic algorithm-neural net realization of any multiple-valued logic function using GA

Minimization of multivalued multithreshold perceptrons using genetic algorithms

Test generation for (sequential) multi-valued logic networks based on genetic algorithm

A review of multiple-valued memory technology

On low cost realization of multiple-valued logic functions

Multiple-valued logic minimization using universal literals and cost tables

A Frontier algorithm for optimization of multiple-valued logic functions

/spl epsiv/-bases of triadic logic operations

Functional entropy and decision trees

Look-up tables (LUTs) for multiple-valued, combinational logic

Multiple-valued floating-gate-MOS pass logic and its application to logic-in-memory VLSI

Residue arithmetic circuits based on the signed-digit multiple-valued arithmetic circuits

Reconfigurable current-mode multiple-valued residue arithmetic circuits

Minimization of incompletely specified regular ternary logic functions and its application to fuzzy switching functions

Upper and lower bounds on the number of fuzzy/c switching functions

On closure operators in fuzzy deductive systems and fuzzy algebras

A study on operations in interval and paired probabilities

Functional-device-based VLSI for intelligent electronic systems

Multiple-valued hyperstructures

A novel nonlinear synapse neuron model guaranteeing a global minimum-Wavelet Neuron

Data envelopment analysis using fuzzy concept

A proposal and an application of a career-mode membership function

Membership functions in automatic harmonization system

On concurrent tests of fuzzy controllers

Generating sets for clones and partial clones

On partial clones containing all idempotent partial operations

Some continuous maps on the space of clones in multiple-valued logic

A finite basis of the set of all monotone partial functions defined over a finite poset

Index of authors

Proceedings 1997 27th International Symposium on Multiple- Valued Logic

Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)

Proceedings 25th International Symposium on Multiple-Valued Logic

Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)

[1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic

[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic

[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic

Proceedings of the Twentieth International Symposium on Multiple-Valued Logic

Proceedings. The Nineteenth International Symposium on Multiple-Valued Logic

[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic

Test generation for (sequential) multi-valued logic networks based on genetic algorithm

Content Provider	IEEE Xplore Digital Library
Author	Keim, M. Drechsler, N. Drechsler, R. Becker, B.
Copyright Year	1998
Description	Author affiliation: Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany (Keim, M.)
Abstract	In this paper we present a test pattern generation tool for combinational Multi-Valued Logic Networks (MVLN) and Sequential Multi-Valued Logic Networks (SMVLN). The test pattern generator is based on a Genetic Algorithm. The tool can generator test patterns with respect to the stuck-at-fault model and skew fault model for SMVLNs with up to some thousand gates. A large set of experimental results is given to demonstrate the efficiency of the approach.
Starting Page	215
Ending Page	220
File Size	93259
Page Count	6
File Format	PDF
ISBN	0818683716
ISSN	0195623X
DOI	10.1109/ISMVL.1998.679435
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-29
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic testing Sequential analysis Multivalued logic Genetic algorithms Circuit faults Circuit testing Test pattern generators Circuit simulation Automatic test pattern generation Circuit synthesis
Content Type	Text
Resource Type	Article
Subject	Computer Science Mathematics

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