NDLI: Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)

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2015 IEEE International Symposium on Multiple-Valued Logic

2014 IEEE 44th International Symposium on Multiple-Valued Logic

2013 IEEE 43rd International Symposium on Multiple-Valued Logic

2012 IEEE 42nd International Symposium on Multiple-Valued Logic

2011 41st IEEE International Symposium on Multiple-Valued Logic

2010 40th IEEE International Symposium on Multiple-Valued Logic

2009 39th International Symposium on Multiple-Valued Logic

38th International Symposium on Multiple Valued Logic (ismvl 2008)

37th International Symposium on Multiple-Valued Logic (ISMVL'07)

36th International Symposium on Multiple-Valued Logic (ISMVL'06)

35th International Symposium on Multiple-Valued Logic (ISMVL'05)

Proceedings. 34th International Symposium on Multiple-Valued Logic

33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.

Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic

Proceedings 31st IEEE International Symposium on Multiple-Valued Logic

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)

Computational neurobiology meets semiconductor engineering

Multi-valued logic pass gate network using neuron-MOS transistors

The synthesis of multiple-valued logic circuits using local-excitation-type neuron models

Multi-input variable-threshold circuits for multi-valued logic functions

The computing capacity of three-input multiple-valued one-threshold perceptrons

MDD-based synthesis of multi-valued logic networks

Fast transforms for multiple-valued input binary output PLI logic

Computation of spectral information from logic netlists

Fault analysis of the multiple valued logic using spectral method

Neural networks: binary monotonic and multiple-valued

Data mining of weak functional decompositions

Multi-valued sub-function encoding in functional decomposition based on information relationships measures

On the number of dependent variables for incompletely specified multiple-valued functions

Some properties of discrete interval truth valued logic

Independence of the axioms of Boolean algebra in multiple-valued logic

On Urquhart's C logic

A new class of fuzzy modifiers

Fuzzy decision diagrams for the representation, analysis and optimization of rule bases

On algebraic foundations of information granulation III. Investigating the HATA-MUKAIDONO approach

Experiments on FPRM expressions for partially symmetric logic functions

Representations of multiple-output switching functions using multiple-valued pseudo-Kronecker decision diagrams

A new algorithm to compute quaternary Reed-Muller expansions

Evolvable hardware: from on-chip circuit synthesis to evolvable space systems

de Morgan bisemilattices

Finite-valued approximations of product logic

Integration of information in four-valued logics under non-uniform assumptions

Lower bound sifting for MDDs

Implementation of multiple-output functions using PQMDDs

Fibonacci decision diagrams and spectral Fibonacci decision diagrams

Cost-analysis of 4-valued unary functions implemented using current-mode CMOS circuits

Implementation of multiple-valued multiplier on GF(3/sup m/) using current mode CMOS

Novel /spl Pi/-type resistor network in D/A converter based on multiple-valued logic

Mod-p decision diagrams: a data structure for multiple-valued functions

Dynamic re-encoding during MDD minimization

Controllability/observability measures for multiple-valued test generation based on D-algorithm

Evolutionary multi-level network synthesis in given design style

An evolutionary computing approach to multilevel logic synthesis using various logic operations

Information theoretic approach to minimization of polynomial expressions over GF(4)

On an architecture of medical image registration system based on multiple-valued logic

Gray scale image compression based on multiple-valued input binary functions, Walsh and Reed-Muller spectra

A four-valued logic B(4) of E(9) for modeling human communication

Structures with many-valued information and their relational proof theory

Demonstration of a novel multiple-valued T-gate using multiple-junction surface tunnel transistors and its application to three-valued data flip-flop

A study on the ternary parallel circuit design with DCG properties based on the matrix equation

Novel resonant-tunneling multiple-threshold logic circuit based on switching sequence detection

Standard CMOS implementation of a multiple-valued logic signed-digit adder based on negative differential-resistance devices

The 2-SAT problem of regular signed CNF formulas

Chaining techniques for automated theorem proving in many-valued logics

High-radix parallel VLSI dividers without using quotient digit selection tables

Properties of independent components of self-motion optical flow

A multilevel-cell 32 Mb flash memory

Hardware implementation of "Supplementary symmetrical logic circuit structure" concepts

Design of a quaternary latch circuit using a binary CMOS RS latch

Low-power dual-rail multiple-valued current-mode logic circuit using multiple input-signal levels

Rigidity problem of autodual clones

On the intersection of maximal partial clones and the join of minimal partial clones

Logic synthesis of controllers for B-ternary asynchronous systems

Silicon single-electron devices and their applications

DRAM-cell-based multiple-valued logic-in-memory VLSI with charge addition and charge storage

An efficient data transmission technique for VLSI systems based on multiple-valued code-division multiple access

Arithmetic-oriented multiple-valued logic-in-memory VLSI based on current-mode logic

A method for approximate equivalence checking

Propagation algorithm of behavior probability in power estimation based on multiple-valued logic

Probabilistic verification of multiple-valued functions

Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)

Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)

Proceedings 1997 27th International Symposium on Multiple- Valued Logic

Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)

Proceedings 25th International Symposium on Multiple-Valued Logic

Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)

[1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic

[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic

[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic

Proceedings of the Twentieth International Symposium on Multiple-Valued Logic

Proceedings. The Nineteenth International Symposium on Multiple-Valued Logic

[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic

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2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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