NDLI: 37th International Symposium on Multiple-Valued Logic (ISMVL'07)

Please wait, while we are loading the content...

2015 IEEE International Symposium on Multiple-Valued Logic

2014 IEEE 44th International Symposium on Multiple-Valued Logic

2013 IEEE 43rd International Symposium on Multiple-Valued Logic

2012 IEEE 42nd International Symposium on Multiple-Valued Logic

2011 41st IEEE International Symposium on Multiple-Valued Logic

2010 40th IEEE International Symposium on Multiple-Valued Logic

2009 39th International Symposium on Multiple-Valued Logic

38th International Symposium on Multiple Valued Logic (ismvl 2008)

37th International Symposium on Multiple-Valued Logic (ISMVL'07)

37th International Symposium on Multiple-Valued Logic - Title page

37th International Symposium on Multiple-Valued Logic - Copyright notice

Message from the Chair

Message from the Program Chair

Conference Committee

Program Committee

Grand Challenges of Nanoelectronics and Possible Architectural Solutions: What Do Shannon, von Neumann, Kolmogorov, and Feynman Have to do with Moore

The Ternary Calculating Machine of Thomas Fowler

Automated Reasoning in Some Local Extensions of Ordered Structures

Reading the Sampling Theorem in Multiple-Valued Logic: A Journey from the (Shannong) Sampling Theorem to the Shannon Decomposition Rule

Model-Characterizing Formulas and Normal Forms in Godel Logics

Spectral Analysis of Special Properties of Ternary Functions

Representations of Elementary Functions Using Edge-Valued MDDs

Experimental Studies on SAT-Based ATPG for Gate Delay Faults

Polynomials as Generators of Minimal Clones

Restriction-Closed Hyperclones

Monoidal Intervals of Partial Clones

Variable Reordering and Sifting for QMDD

GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits

A Generalization of the Deutsch-Jozsa Algorithm to Multi-Valued Quantum Logic

The Genetic Code as a Multiple-Valued Function and Its Implementation Using Multilayer Neural Network Based on Multi-Valued Neurons

Non-deterministic Multi-valued Matrices for First-Order Logics of Formal Inconsistency

New Fastest Linearly Independent Transforms over GF(3)

Inversion/Division in Galois Field Using Multiple-Valued Logic

Boolean Functions of Low Polynomial Degree for Quantum Query Complexity Theory

Quantum Robots for Teenagers

Quantum Mechanical Model of Emotional Robot Behaviors

Quantum Realization of Some Ternary Circuits Using Muthukrishnan-Stroud Gates

2-SAT Problems in Some Multi-Valued Logics Based on Finite Lattices

A Complete Resolution Calculus for Signed Max-SAT

Efficient Algorithm for Calculation of Quaternardy Fixed Polarity Arithmetic Expansions

Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices

Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits

Equalization Techniques for Multiple-Valued Data Transmission and Their Application

The Rough Powerset Monad

Exploiting Homogeneous Dual Polarity Routes in Implementation of Algorithms for Optimization of Galois Field Expressions for Ternary Functions

Automated Reasoning Algorithm for Linguistic Valued Lukasiewicz Propositional Logic

Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams

On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--

On the Axiomatization of Generalized Entropic Metrics

Characterization of Partial Sheffer Functions in 3-Valued Logic

Power Indexes in Voting Systems and Multiple-Valued Logic

A Ternary Analog-to-Digital Converter System

Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate Devices

Fault Tolerant CMOS Logic Using Ternary Gates

Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation

An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays

Linearization of Ternary Decision Diagrams by Using the Polynomial Chrestenson Spectrum

Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC

Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor

Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme

Classifications and Enumeration of Bases in P_{3}(2)

Simulation of Gate Circuits with Feedback in Multi-Valued Algebras

Properties and Fast Algorithms for Ternary Walsh Transform

Weighted and Ordered Direct Cover Algorithms for Minimization of MVL Functions

Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions

Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL

Limits to a Correct Evaluation in RTD-Based Quaternary Inverters

Evaluation and Comparison of Threshold Logic Gates

Towards First-Order Symbolic Trajectory Evaluation

Survey of Stochastic Computation on Factor Graphs

A Note on Possible Applications of Fourier Representations in Circuit Design over Reprogrammable Technological Platforms

Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design

High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction

Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process

36th International Symposium on Multiple-Valued Logic (ISMVL'06)

35th International Symposium on Multiple-Valued Logic (ISMVL'05)

Proceedings. 34th International Symposium on Multiple-Valued Logic

33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.

Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic

Proceedings 31st IEEE International Symposium on Multiple-Valued Logic

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)

Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)

Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)

Proceedings 1997 27th International Symposium on Multiple- Valued Logic

Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)

Proceedings 25th International Symposium on Multiple-Valued Logic

Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)

[1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic

[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic

[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic

Proceedings of the Twentieth International Symposium on Multiple-Valued Logic

Proceedings. The Nineteenth International Symposium on Multiple-Valued Logic

[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in