NDLI: Minimum leakage vector computation using weighted partial MaxSAT

Content Provider	IEEE Xplore Digital Library
Author	Singh, A. Gulati, K. Khatri, S.P.
Copyright Year	2010
Description	Author affiliation: Strategic CAD Laboratories, Intel Corporation, Hillsboro OR 97124, USA (Gulati, K.) \|\| Department of Electrical & Computer Engineering, Texas A&M University, College Station TX 77843, USA (Singh, A.; Khatri, S.P.)
Abstract	Aggressive scaling of CMOS technology has enabled faster and smaller designs but has posed new challenges. In the deep-submicron era, leakage power has become a major contributor to the overall power dissipation of an IC. In this paper, we present a weighted partial Max-SAT (WPMax-SAT) based approach to find the minimum leakage vector (MLV) of a combinational design. In its exact form, this technique computes the input vector which gives the lowest leakage for a combinational design. For large designs, the exact WPMax-SAT based technique may require large runtimes. Therefore, for such designs, the exact technique is run for a fixed amount of time followed by a guided random search around the best leakage vector computed by the WPMax-SAT solver. We also present a variant of our approach in which the MLV is generated by including the effect of random variations in leakage due to variations in process, voltage and temperature (PVT). Experimental results on ISCAS85 and MCNC91 benchmark circuits show that for larger circuits on average, our method reports a 3.62% improvement in mean, 4.20% improvement in standard deviation and 3.67% improvement in μ + 3✻σ leakage of the circuit under PVT variations, compared to a random vector based MLV determination approach (with the same runtime as the random vector based approach).
Starting Page	201
Ending Page	204
File Size	495419
Page Count	4
File Format	PDF
ISBN	9781424477715
ISSN	15483746
e-ISBN	9781424477739
DOI	10.1109/MWSCAS.2010.5548692
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuits Subthreshold current Threshold voltage CMOS technology Power dissipation Runtime Energy consumption Leakage current Dynamic voltage scaling Power engineering computing
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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