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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ferre, A. Figueras, J. |
| Copyright Year | 1998 |
| Description | Author affiliation: Dept. d'Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain (Ferre, A.) |
| Abstract | A model to statistically characterize the leakage power of CMOS digital circuits is presented. Based on the subthreshold leakage characterization at transistor and cell level, the leakage power consumption of a standard cell circuit is obtained. Also, in order to estimate the leakage power variability for a fixed state, a model of variations due to process is introduced. Using these models, the P/sub LEAK/ distribution is found to be asymmetric around the nominal value showing a long tail for high consuming circuits. The model has been found effective in evaluating the correlation of leakage power with other performance specs, in particular delay. We have shown that an IC with short L, and therefore, with high P/sub LEAK/ will be faster than nominal ones and an IC with long L, and therefore, with low P/sub LEAK/ will be slower. Predicted results are consistent with available experimental data. |
| Starting Page | 185 |
| Ending Page | 188 |
| File Size | 391809 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780350081 |
| DOI | 10.1109/ICECS.1998.814859 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1998-09-07 |
| Publisher Place | Portugal |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | CMOS technology CMOS digital integrated circuits Semiconductor device modeling Subthreshold current Energy consumption Leakage current Threshold voltage Digital circuits Power supplies Dynamic voltage scaling |
| Content Type | Text |
| Resource Type | Article |
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