NDLI: An automated design tool for analog layouts

Content Provider	IEEE Xplore Digital Library
Author	Lihong Zhang Kleine, U. Yingtao Jiang
Copyright Year	1993
Abstract	In this paper, a layout synthesis tool for the design of analog integrated circuits (ICs) is presented. This tool offers great flexibility that allows analog circuit designers to bring their special design knowledge and experiences into the synthesis process to create high-quality analog circuit layouts. Different from conventional layout systems that are limited to the optimization of single devices, our layout generation tool attempts to optimize more complex modules. This tool includes a complete tool suite that covers the following three major analog physical designs stages. 1) Module Generation: designers can develop and maintain their own technology- and application-independent module generators for subcircuits using an in-house developed description language. 2) Placement: a two-stage placement technique, tailored for the analog placement design, is proposed. In particular, this placement algorithm features a novel genetic placement stage followed by a fast simulated reannealing scheme. 3) Routing: the minimum-Steiner-tree-based global routing is developed, and it is actually integrated into the placement procedure to improve reliability and routability of the placement solutions. Following the global routing, a compaction-based constructive detailed routing finally completes the interconnection of the entire layout. Several testing circuits have been applied to demonstrate the design efficiency and the effectiveness of this tool. Experimental results show that this new layout tool is capable of producing high quality layouts comparable to those manually done by layout experts but with much less design time
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	881
Ending Page	894
Page Count	14
File Size	2282107
File Format	PDF
ISSN	10638210
Volume Number	14
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analog circuits Design automation Routing Circuit testing Integrated circuit synthesis Analog integrated circuits Circuit simulation Circuit synthesis Genetics Integrated circuit reliability integrated circuit layout Algorithms analog integrated circuits (ICs) design automation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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