NDLI: A tool for automated analog CMOS layout module generation and placement

Content Provider	IEEE Xplore Digital Library
Author	Khademsameni, P. Syrzycki, M.
Copyright Year	2002
Description	Author affiliation: Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada (Khademsameni, P.; Syrzycki, M.)
Abstract	Layout design is a very important step of the analog CMOS IC design flow. Good layout quality featuring low susceptibility to digital noise and low sensitivity to process variation requires layout designers with significant expertise. The layout optimization process needs new CAD tools that will quickly generate multiple versions of analog CMOS IC layouts for parasitic extraction and post-layout simulation. We propose a new CAD tool that will produce analog CMOS layout modules in a given CMOS process. Multiple use of the tool with different control parameters results in obtaining several versions of CMOS layout modules of a single circuit. These layouts can be used for post-layout simulation and layout optimization. This paper presents the tool's architecture and examples of its use for analog CMOS layout design.
Sponsorship	Dept. Electr. & Comput. Eng. Faculty of Graduate Studies Faculty of Eng. TRLabs Internet Innovation Centre NRC Inst. Biodiagnostics APEGM IEEE Winnipeg Sec. IEEE Canada & IEEE Manitoba Hydro Vansco Electron. Bristol Aerosp. Nygard Int. Norsat
Starting Page	416
Ending Page	421
File Size	609682
Page Count	6
File Format	PDF
ISBN	0780375149
ISSN	08407789
DOI	10.1109/CCECE.2002.1015261
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-12
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analog circuits Design automation CMOS analog integrated circuits CMOS process Circuit simulation Circuit noise Analog integrated circuits CMOS integrated circuits Digital circuits Integrated circuit layout
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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