NDLI: SXDR64 — multichannel low noise ASIC for CdTe and GaAs detectors

Content Provider	IEEE Xplore Digital Library
Author	Kachel, M. Grybos, P. Kmon, P. Szczygiel, R.
Copyright Year	2009
Description	Author affiliation: Department of Measurements and Instrumentation, University of Science and Technology - AGH, Krakow, Poland (Kachel, M.; Grybos, P.; Kmon, P.; Szczygiel, R.)
Abstract	A 64-channel ASIC called SXDR64 has been developed. The ASIC is aimed to work with DC coupled CdTe and GaAs detectors. Each channel of ASIC consists of charge sensitive amplifier, pole-zero cancellation circuit, $4^{th}$ order shaper with programmable gain and peaking time from 115 ns to 380 ns, base-line restorer, two independent discriminators and two 20-bit counters. The IC control and readout of the data are done via LVDS drivers/receivers. Circuit can operate with input leakage currents in the range from −5 nA up to 10 nA and the frequency of input pulses up to 1 MHz. Simulated equivalent noise charge of the front-end electronics for 3 pF detector capacitance, detector leakage current of 500 pA and peaking time Tp=380 ns is 123 electrons rms. The ASIC is designed in CMOS 0.35 µm technology and its total area is 4800 × 5000 $µm^{2}.$
Starting Page	324
Ending Page	327
File Size	590767
Page Count	4
File Format	PDF
ISBN	9781424447985
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-25
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Tech Univ of Lodz
Subject Keyword	Multi-stage noise shaping multichannel ASIC Gallium arsenide front-end electronics Leak detection GaAs CdTe matching Application specific integrated circuits Coupling circuits Detectors CMOS technology Noise cancellation Leakage current Circuit noise
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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