NDLI: An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators

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An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators

Content Provider	IEEE Xplore Digital Library
Author	Ramirez-Angulo, J. Kalyani-Garimella, L.M. Garimella, A. Garimella, S.R.S. Lopez-Martin, A. Carvajal, R.G.
Copyright Year	2008
Description	Author affiliation: New Mexico State Univ., Las Cruces (Ramirez-Angulo, J.; Kalyani-Garimella, L.M.; Garimella, A.; Garimella, S.R.S.; Lopez-Martin, A.; Carvajal, R.G.)
Abstract	A rail-to-rail differential input stage with programmable threshold levels and offset compensation is introduced. Applications for the implementation of differential and double differential comparators are discussed. Experimental results obtained from a MOSIS 0.5 mum CMOS technology test chip are shown that validate rail-to-rail operation with a 1.5 V supply voltage.
Starting Page	294
Ending Page	299
File Size	1985320
Page Count	6
File Format	PDF
ISBN	0769530834
ISSN	10639667
DOI	10.1109/VLSI.2008.30
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-04
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Rail to rail inputs Very large scale integration CMOS technology Low voltage Circuit testing Rail to rail operation Switching circuits Switched capacitor circuits MOS devices Batteries
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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