NDLI: 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

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2015 28th International Conference on VLSI Design

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

Table of contents

Message from the Steering Committee Chair

Welcome Message

Message from the President, VLSI Society of India

Message from the Tutorial Co-Chairs

Message from the User/Designer Track Chair

VLSI Design Conference Steering Committee (2013)

VLSI Design 2013 Conference Committee

Program Committee

[Plenary talks - 11 abstracts]

About the cover from the Publication Co-Chairs

VLSI Design Conference History

Embedded Systems Design Conference History

Conference Program

Call for Papers -- VLSI Design and Test Symposium (VDAT 2014)

Tutorial T1: Ambient Intelligence through Internets-of-Things - An Application Development Approach

Tutorial T2A: Scheduling Issues in Embedded Real-Time Systems

Tutorial T2B: Cost/Application/Time to Market Driven SoC Design and Manufacturing Strategy

Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices

Tutorial T3B: Engineering Change Order (ECO) Phase Challenges and Methodologies for High Performance Design

Tutorial T4: All You Need to Know about Hardware Trojans and Counterfeit ICs

Tutorial T5: Microfluidic Biochips: Connecting VLSI and Embedded Systems to the Life Sciences

Tutorial T6A: Pedagogy of Negative Feedback Circuits

Tutorial T6B: Embedded Memory Design for Future Technologies: Challenges and Solutions

Tutorial T7A: Techniques for Network-on-Chip (NoC) Design and Test

Tutorial T7B: Network on Chips - The Journey Overview

Tutorial T8A: Realization of RF Front-End for a Cognitive Radio

A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits

Analytical Modeling of 3D Stacked IC Yield from Wafer to Wafer Stacking with Radial Defect Clustering

Process-Variation Aware Multi-temperature Test Scheduling

Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown

Debug Automation for Synchronization Bugs at RTL

Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation

SAT-Based Test Pattern Generation with Improved Dynamic Compaction

Efficient SAT-Based Circuit Initialization for Larger Designs

A Coverage Guided Mining Approach for Automatic Generation of Succinct Assertions

Effective Liveness Verification Using a Transformation-Based Framework

Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism

All-SAT Using Minimal Blocking Clauses

CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities

A Cube-Aware Compaction Method for Scan ATPG

Scalable Test Generation by Interleaving Concrete and Symbolic Execution

Application of Test-View Modeling to Hierarchical ATPG

A New Sensitivity-Driven Process Variation Aware Self-Repairing Low-Power SRAM Design

Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error Resilience

A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units

Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths

Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories

Energy Efficient Memory Decoder Design for Ultra-low Voltage Systems

A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist

Minimizing Power and Skew in VLSI-SoC Clocking with Pulsed Resonance Driven De-skewing Latches

Efficient Two-Phase Approaches for Branch-and-Bound Style Resource Constrained Scheduling

Inserting Placeholder Slack to Improve Run-Time Scheduling of Non-preemptible Real-Time Tasks in Heterogeneous Systems

Hardware Implementation of Real-Time, High Performance, RCE-NN Based Face Recognition System

EME Electric Supervision Embedded on Gas Panel with Microshock Dangerousness Degree

Design of AFE and PWM Drive for Lithium-Ion Battery Management System for HEV/EV System

Process Disturbance Analyzer for Nuclear Reactors

Design and Implementation of Safety Logic with Fine Impulse Test System for a Nuclear Reactor Shutdown System

Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core

Process Synchronization in Multi-core Systems Using On-Chip Memories

TECS: Temperature- and Energy-Constrained Scheduling for Multicore Systems

Challenges in Implementing Cache-Based Side Channel Attacks on Modern Processors

Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization

NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-core Systems

CARM: Congestion Adaptive Routing Method for On Chip Networks

Knowledge-Guided Methodology for Third-Party Soft IP Analysis

Pre-mapping Algorithm for Heterogeneous MPSoCs

Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR)

Temperature Minimization Using Power Redistribution in Embedded Systems

Process Variation Aware Synthesis of Application-Specific MPSoCs to Maximize Yield

Hard versus Soft Software Defined Radio

Interfacing Synchronous and Asynchronous Domains for Open Core Protocol

Control Mechanism to Solve False Blocking Problem at MAC Layer in Wireless Sensor Networks

Architecture for Blocking Detection in Wireless Video Source Authentication

A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm

Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs

A Hardware Intensive Approach for Efficient Implementation of Numerical Integration for FPGA Platforms

Embedded Complex Floating Point Hardware Accelerator

A Power Efficient Video Encoder Using Reconfigurable Approximate Arithmetic Units

QUICKRECALL: A Low Overhead HW/SW Approach for Enabling Computations across Power Cycles in Transiently Powered Computers

Configurable Systolic Matrix Multiplication

ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs

Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform

Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology

Scalable Low Power FFT/IFFT Architecture with Dynamic Bit Width Configurability

A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter

Global Routing Using Monotone Staircases with Minimal Bends

Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire

On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions

Obstacle Avoiding Rectilinear Clock Tree Construction with Skew Minimization

Layout-Aware Delay Variation Optimization for CNTFET-Based Circuits

Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations

Small Signal Nonquasi-static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry

Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor

Statistical Modeling of Glitching Effects in Estimation of Dynamic Power Consumption

BSIM6 -- Benchmarking the Next-Generation MOSFET Model for RF Applications

Analysis of Nanoscale Strained-Si/SiGe MOSFETs including Source/Drain Series Resistance through a Multi-iterative Technique

An ABCD Parameter Based Modeling and Analysis of Crosstalk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects

Performance Optimization and Parameter Sensitivity Analysis of Ultra Low Power Junctionless MOSFETs

Improvements to Negative-C Compensation Based Amplifiers for Broadband Applications

An Adaptive Inductorless Continuous Time Equalizer for Gigabit Links in 0.13 um CMOS

On Dependence of Amplitude Noise versus Offset Frequency in LC Oscillators

A 1 V, Sub-mW CMOS LNA for Low-Power 1 GHz Wide-Band Wireless Applications

Low Power Single Amplifier Voltage Regulator

Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS

FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage

Operand Isolation with Reduced Overhead for Low Power Datapath Design

High-Speed, Low-Power Quasi Delay Insensitive Handshake Circuits Based on FinFET Technology

Active Cooling Technique for Efficient Heat Mitigation in 3D-ICs

Improved Design Methodology for the Development of Electrically Actuated MEMS Structures

Correctness Checking of Bio-chemical Protocol Realizations on a Digital Microfluidic Biochip

A Novel Wire Planning Technique for Optimum Pin Utilization in Digital Microfluidic Biochips

Output Impedance as Figure of Merit to Predict Transient Performance for Embedded Linear Voltage Regulators

A Time-Based Low Voltage Body Temperature Monitoring Unit

Trimless, PVT Insensitive Voltage Reference Using Compensation of Beta and Thermal Voltage

A Low Power CMOS Imager Based on Distributed Compressed Sensing

All Optical Reversible Multiplexer Design Using Mach-Zehnder Interferometer

Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits

Design of Dedicated Reversible Quantum Circuitry for Square Computation

An Optimized Design of Reversible Quantum Comparator

Light Load Efficiency Improvement in High Frequency DC-DC Buck Converter Using Dynamic Width Segmentation of Power MOSFET

Histogram Based Deterministic Digital Background Calibration for Pipelined ADCs

A Power Efficient Fully Differential Back Terminated Current-Mode HDMI Source

An Adaptive Body-Biased Clock Generation System in 28nm CMOS

Publisher's Information

2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems

2012 25th International Conference on VLSI Design

2011 24th Internatioal Conference on VLSI Design

2010 23rd International Conference on VLSI Design

2009 22nd International Conference on VLSI Design

21st International Conference on VLSI Design (VLSID 2008)

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design

17th International Conference on VLSI Design. Proceedings.

16th International Conference on VLSI Design, 2003. Proceedings.

VLSI Design 2001. Fourteenth International Conference on VLSI Design

VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)

Proceedings Eleventh International Conference on VLSI Design

Proceedings Tenth International Conference on VLSI Design

Proceedings of 9th International Conference on VLSI Design

Proceedings of the 8th International Conference on VLSI Design

Proceedings of 7th International Conference on VLSI Design

The Sixth International Conference on VLSI Design

The Fifth International Conference on VLSI Design

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