NDLI: A 100 tap FIR/IIR analog linear-phase lowpass filter

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2015 Symposium on VLSI Circuits (VLSI Circuits)

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Integrating intelligence on silicon electronic systems. An inter-University cooperative research project for innovative process, device, circuit, and system technologies

Active matrix LCDs: a clear, bright future

A 0.4 /spl mu/m 1.4 ns 32b dynamic adder using non-precharge multiplexers and reduced precharge voltage technique

A 500 MHz 1-stage 32 bit ALU with self-running test circuit

A 375 MHz 1 /spl mu/m CMOS 8-bit multiplier

A 286 MHz 64-bit floating point multiplier with enhanced CG operation

A 2.25 gbytes/s 1 Mbit smart cache SRAM

A 90 MHz 16 Mbit system integrated memory with direct interface to CPU

A 2-ns, 5-mW, synchronous-powered static-circuit fully associative TLB

A current direction sense technique for multi-port SRAMs

Driving source-line (DSL) cell architecture for sub-1-V high-speed low-power applications

A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-memory

Low power Gb/s CMOS interfaces

Capacitance coupling immune, transient sensitive accelerator for resistive interconnection signals of sub-quarter micron ULSI

Substrate noise reduction using active guard band filters in mixed-signal integrated circuits

A 0.25 mW sigma-delta modulator for voice-band applications

Power-efficient metastability error reduction in CMOS flash A/D converters

Voltage-comparator-based measurement of equivalently sampled substrate noise waveform in mixed-signal integrated circuits

A post processing method for reducing substrate coupling in mixed-signal integrated circuits

CMOS stress sensor circuits using piezoresistive field-effect transistors (PIFETs)

Combined air humidity and flow CMOS microsensor with on-chip 15 bit sigma-delta A/D interface

Design aspects of 10 to 40 Gb/s digital and analog Si-bipolar ICs

"Graphics synthesizer" for video game applications

A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing

A bit-parallel block-parallel functional memory type parallel processor LSI for fast addition and multiplication

A 16 bit low-power-consumption digital signal processor using a 80 MOPS redundant binary MAC

A single chip MPEG1 decoder

A 3.3 V 16 Mbit DRAM-compatible flash memory

A double-level-V/sub th/ select gate array architecture for multi-level NAND flash memories

A novel sense amplifier for flexible voltage operation NAND flash memories

A stable programming pulse generator for high-speed programming single power supply voltage flash memories

An on-chip high-voltage generator circuit for EEPROMs with a power supply voltage below 2 V

A 5V-only 16M flash memory using a contactless array of source-side injection cells

Cell-plate-line and bit-line complementarily sensed (CBCS) architecture for ultra low-power non-destructive DRAMs

A parallel processor for neural networks

A 2.5-Gb/sec 15-mW BiCMOS clock recovery circuit

A 250-622 MHz deskew and jitter-suppressed clock buffer using a frequencyand delay-locked two-loop architecture

An analog integrated polyphase filter for a high performance low-IF receiver

A 2V BiCMOS receiver chip for L-S-C band personal networks

A 100 tap FIR/IIR analog linear-phase lowpass filter

A MOSFET-only continuous-time 560 kHz tunable bandpass filter

A CMOS limiting amplifier and signal-strength indicator

17 GHz-bandwidth 17 dB-gain 0.3 /spl mu/m-HEMT low-power limiting amplifier

A 250 mV bit-line swing scheme for a 1 V 4 Gb DRAM

A crossing charge recycle refresh scheme with a separated driver sense-amplifier for Gb DRAMs

SOI-DRAM circuit technologies for low power high speed multi-giga scale memories

A 286 mm/sup 2/ 256 Mb DRAM with X32 both-ends DQ

Fault-tolerant designs for 256 Mb DRAM

A novel power-off mode for a battery-backup DRAM

A mixed-mode voltage-down converter with impedance adjustment circuitry for low-voltage wide-frequency DRAMs

A low noise 32 bit-wide 256 M synchronous DRAM with column-decoded I/O line

Statistical electromigration budgeting for reliable design and verification in a 300-MHz microprocessor

30 GHz static 2:1 frequency divider and 46 Gb/s multiplexer/demultiplexer ICs in a 0.6 /spl mu/m Si bipolar technology

A novel BiCMOS circuit using a base boost technique for low voltage application

An accurate quasi-saturation BJT model for very-high-frequency analog/digital applications

Pass transistor based gate array architecture

A 1-V high-speed MTCMOS circuit scheme for power-down applications

A low-power bipolar circuit for Gbit/s LSIs-current mirror control logic (CMCL)

Efficient charge recovery logic

Proceedings of 1994 IEEE Symposium on VLSI Circuits

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1992 Symposium on VLSI Circuits Digest of Technical Papers

1991 Symposium on VLSI Circuits

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