NDLI: A 1-V high-speed MTCMOS circuit scheme for power-down applications

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A 1-V high-speed MTCMOS circuit scheme for power-down applications

Content Provider	IEEE Xplore Digital Library
Author	Shigematsu, S. Mutoh, S. Matsuya, Y. Yamada, J.
Copyright Year	1995
Description	Author affiliation: NTT LSI Labs., Atsugi, Japan (Shigematsu, S.; Mutoh, S.; Matsuya, Y.; Yamada, J.)
Abstract	A new MTCMOS concept is proposed for power-down applications. This concept realises a new circuit scheme to hold data during the power-down period in which the power is not supplied. Low-power, high-speed performance are achieved by separating the holding circuit from the critical path. A scan register has been developed based on this concept. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-/spl mu/m CMOS technology.
Starting Page	125
Ending Page	126
File Size	225387
Page Count	2
File Format	PDF
ISBN	0780025990
DOI	10.1109/VLSIC.1995.520717
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-06-08
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sleep Latches Clocks Large scale integration Power supplies MOSFETs CMOS technology Leakage current Logic circuits Automatic testing
Content Type	Text
Resource Type	Article

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