NDLI: A CMOS multi-bit sigma-delta modulator for video applications

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Table of contents

Intelligent networks: Foundation for information societies

Technology trends and design challenges for microprocessor design

Wireless integrated network sensors: Low power systems on a chip

The impact of shrinking sizes on circuit design

System and circuit aspects of nanoelectronics

Low-cost all-polymer integrated circuits

The future of communications

Digital goes analog

RFIC packaging and test: How will we cut costs?

A 0.25 µm CMOS I/Q-channel downconversion mixer with active coil for DCS-1800 applications

A high linearity, single-ended input double-balanced mixer in 0.25µm CMOS

A 0.25 µm CMOS fully integrated IF-baseband-strip for a single superheterodyne GSM receiver

A high-speed, direct up-conversion transmitter for cable applications using very linear 0.5 µm "Cold" CMOS mixers

Transformerless line interface solution for baseband modems

A 1.9GHz 1W CMOS class E power amplifier for wireless communications

A 5.5-GHz low noise amplifier in SiGe BiCMOS

A dual-band transceiver for GSM and DCS1800 applications

Resonance-mode selection and crosstalk elimination using resonator-synchronised relaxation oscillators

A Q=100 SC bandpass filter

A coupled sawtooth oscillator combining low jitter and high control linearity

High efficiency charge pump circuit for negative high voltage generation at 2 V supply voltage

A new CMOS on-chip high-voltage generator

Compact low-voltage PTAT-current source and bandgap-reference circuits

A CMOS class-AB instrumentation amplifier for micropower applications

Low-power bandgap references featuring DTMOSTs

Serial interface macrocells for 2.5 Gb/s in 0.35µm CMOS

16-Gbit/s measurements on a 0.8-µm CMOS sub-sampling circuit

A high speed 3.3V IO buffer with 1.9V tolerant CMOS process

A 600MHz superscalar floating point processor

A 5.2 nS cycle time floating point unit macrocell

An area-efficient circuit concept for dynamical conflict management of N-port memories with multi-GBit/s access bandwidth

A multimedia-oriented embedded RISC processor with a rambus DRAM controller

A digital clock generator for an ATM switch implemented with multiphase clock

Digital controlled variable gain amplifier (DVGA) for IF to digital conversion

A combined LC/gmC 4th order continuous-time bandpass ΣΔ modulator

A 16 mW, 120 dB linear switched-capacitor delta-sigma modulator with dynamic biasing

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A 3.3 V 15-bit delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL-applications

A 800 MHz ultra low glitch energy 6-bit CMOS D/A converter

A real-time digital VCR encode/decode and MPEG2 decode LSI implemented on a dual-issue RISC processor

A 16-bit D/A interface with sinc approximated semidigital reconstruction filter and reduced number of coefficients

MIGHTI: A high performance 16-bit DSP for mobile communication applications

Low cost on-die CMOS distributed voltage regulation for microcontrollers

A 1.0V 180Mhz 85µW/Mhz 8k×16b SRAM in a standard 0.25µm CMOS

Low power SOI CMOS multipliers : 2D vs. 3D

SACHEM, a versatile DMT–based modem transceiver for ADSL

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A smart range image sensor

Smart 2048–pixel linear CMOS image sensor

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A CD analog front–end in BiCMOS technology

A CMOS IC for X–ray computed tomography

Monolithic data circuit-terminating unit (DCU) for a one-wire vehicle network

IC for interbus loop system

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An 8 bit, 200Ms/s, full Nyquist, 3.3V, differential interpolated flash A/D converter in BiCMOS technology

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On the evaluation of phase noise in frequency dividers

A GSM demodulator based on a Delta–Sigma frequency discriminator with improved input sensitivity

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Reduction of intrinsic 1/f device noise in a CMOS ring oscillator

A programmable analog polynomial predistortion circuit for linearising radio transmitters

A 0.7 µm CMOS 1Gb/s optical receiver with rail–to–rail output swing

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A circuit for the correction of pixel defects in image sensors

A high frame rate image sensor in standard CMOS–technology

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Design of spiral inductors on silicon substrates with a fast simulator

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A 155 Mbit/s fully digital bit synchronizer

D–FIRE: A DAB receiver system on a chip

A 2.4 GHz CMOS VCO with MCM–inductor

Maximum–likelihood PPM frame synchronization

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A study of CMOS 2.0V low power pager receiver for the $FLEX^{TM}paging$ system

A comparison between two 1.8GHz CMOS VCOs tuned by different varactors

A low switching noise power supply technique for CMOS IC's

A 1–Volt 300 MHz fully integrated oscillator

Current–ratio temperature compensation in bipolar relaxation oscillator

An enhanced colpitts UHF oscillator for TV tuners

A 2.7V elliptical all–MOS gC–OTA filter

Design and application of SOI CMOS OTAs for high–temperature environments

Adaptive compensation of analog circuit imperfections for cascaded delta–sigma analog–to–digital converters

An 8–bit resolution, 12–bit accuracy, 500 MS/s update rate, sub–pV.s glitch energy CMOS D/A converter

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A sub–binary–weighted current calibration technique for a 2.5V 100MS/s 8bit ADC

A 10-bit 20-Msample/s sub-ranging ADC for low-power and low-voltage applications

A threshold logic full adder based on resonant tunneling transistors

Signal–transition graph–based design of speed–independent CMOS circuits

VLIW architectures for low–power processors: A first evaluation

A 400MHz 160-word × 64-bit 14-port floating-point register file macrocell for a superscalar RISC processor

Hardware for computing modular multiplication algorithm

A 2.0Gbps multiplexer and a 2.7Gbps demultiplexer using 0.35µm SOI–CMOS technology

A 1–V 20–ns 512–Kbit MT–CMOS SRAM with auto–power–cut scheme using dummy memory cells

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Die stress characterization using arrays of CMOS sensors

A low noise cryogenic CMOS preamplifier for high critical temperature superconducting IR and FIR sensors

A four–channel transimpedance amplifier for CD front–end

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Effect-oriented modelling of noise in relaxation oscillators

Madematching: Methodology and tool for matching simulation

Fast phase noise analysis method for noise optimisation of oscillators

Overcoming insufficiencies of first order mismatch modeling

Proceedings of the 23rd European Solid-State Circuits Conference

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A CMOS multi-bit sigma-delta modulator for video applications

Content Provider	IEEE Xplore Digital Library
Author	Vink, J. van Rens, J.
Copyright Year	1998
Description	Author affiliation: Philips Research Laboratories, Eindhoven, Netherlands (Vink, J.)
Abstract	This paper describes the design of a sigma-delta modulator with 5-bit quantizer for analog to digital conversion in video applications. A single poly, 0.35 µm CMOS process is used. Most of the quantization noise of a sigma-delta modulator is shifted to higher frequencies by noise shaping. The resulting output spectrum corresponds well with the noise sensitivity of the human eye which is less sensitive to high frequency noise. The realized sigma-delta modulator has an excellent low frequency performance, the DNL is 0.51 LSB@10 bit level and the integrated noise up to 1 MHz is 60 dB below the maximum signal power. The SNR (noise integrated over total band of 6.75 MHz) is 43.6 dB.
Starting Page	164
Ending Page	167
File Size	395716
Page Count	4
File Format	PDF
DOI	10.1109/ESSCIR.1998.186234
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-09-22
Publisher Place	The Netherlands
Access Restriction	Subscribed
Rights Holder	Editions Frontieres
Subject Keyword	Delta-sigma modulation Low-frequency noise Noise shaping Frequency Digital modulation Analog-digital conversion CMOS process Quantization Multi-stage noise shaping Humans
Content Type	Text
Resource Type	Article

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