NDLI: A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless Transmitters

Content Provider	IEEE Xplore Digital Library
Author	Parikh, V.K. Balsara, P.T. Eliezer, O. Mehta, J.
Copyright Year	2007
Description	Author affiliation: Dept. of Electr. Eng., Texas Univ., Dallas, TX (Parikh, V.K.; Balsara, P.T.)
Abstract	Digital sigma-delta (SigmaDelta) modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90nm CMOS digital low-pass SigmaDelta modulator, which has lower quantization noise and lower power consumption compared to other recent structures. A conventional digital SigmaDelta structure uses a 1-bit quantizer and generates very high quantization noise at higher frequencies. In this work, we present a low-pass digital SigmaDelta architecture with a multi-bit quantizer, which achieves very low in-band as well as out-of-band quantization noise levels. It is shown that the structure can be run at half the frequency while meeting the required noise performance and essentially delivering a better power-performance trade-off. The proposed architecture, along with the original 1-bit quantizer structure, has been synthesized in a 90nm CMOS process. Area and power consumption results are presented and a comparison between a commonly used structure and the proposed one is provided.
Starting Page	3275
Ending Page	3278
File Size	546306
Page Count	4
File Format	PDF
ISBN	1424409209
DOI	10.1109/ISCAS.2007.378210
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Quantization Delta-sigma modulation Digital modulation Transmitters Energy consumption Frequency Data conversion Noise generators Noise level CMOS process
Content Type	Text
Resource Type	Article

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