NDLI: HEVC inverse transform architecture utilizing coefficient sparsity

Content Provider	IEEE Xplore Digital Library
Author	Abeydeer, M. Pasqual, A.
Copyright Year	2015
Description	Author affiliation: Dept. of Electron. & Telecommun. Eng., Univ. of Moratuwa, Moratuwa, Sri Lanka (Abeydeer, M.; Pasqual, A.)
Abstract	The inverse transform function of the HEVC Decoder has grown greatly in complexity with the addition of larger transform sizes and recent works have focused on efficient architectures that can achieve the required throughput. In this work we make the observation that a majority of the coefficients in a typical transform operation is zero, and therefore has no impact on the final outcome. We propose an architecture that can efficiently operate on such sparse matrices and introduce a scheduling strategy which completes a 2D IDCT with bare minimum iterations, with the added advantage of being able to integrate seamlessly with the entropy decoder without a coefficient reordering buffer. Experiments show that although the performance of this approach is scalable with the bit rate, a 120 MHz operating frequency is sufficient to handle QHD @ 48 Mbps, which is less than one third of the frequency requirement of prior work.
Starting Page	4848
Ending Page	4852
File Size	948206
Page Count	5
File Format	PDF
e-ISBN	9781479983391
DOI	10.1109/ICIP.2015.7351728
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-27
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Random access memory Laplace equations Entropy Discrete cosine transforms Throughput
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Energy and area-efficient hardware implementation of HEVC inverse transform and dequantization

Low-cost video transform for HEVC

Opencl parallelization of the HEVC de-quantization and inverse transform for heterogeneous platforms

Zero coefficient-aware fast IQ-IDCT algorithm

Acceleration of HEVC transform and inverse transform on ARM NEON platform

Fully pipelined DCT/IDCT/Hadamard unified transform architecture for HEVC Codec

Improvement of normality and orthogonality in HEVC transform bases

A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs

Unified forward+inverse transform architecture for HEVC

HEVC inverse transform architecture utilizing coefficient sparsity

Similar Documents

Energy and area-efficient hardware implementation of HEVC inverse transform and dequantization

Low-cost video transform for HEVC

Opencl parallelization of the HEVC de-quantization and inverse transform for heterogeneous platforms

Zero coefficient-aware fast IQ-IDCT algorithm

Acceleration of HEVC transform and inverse transform on ARM NEON platform

Fully pipelined DCT/IDCT/Hadamard unified transform architecture for HEVC Codec

Improvement of normality and orthogonality in HEVC transform bases

A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs

Unified forward+inverse transform architecture for HEVC

HEVC inverse transform architecture utilizing coefficient sparsity