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Content Provider | IEEE Xplore Digital Library |
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Author | Chieh-Yang Liu Wen-Quan He Yung-Ming Chang Yuan-Ho Chen |
Copyright Year | 2014 |
Description | Author affiliation: Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Taoyuan, Taiwan (Chieh-Yang Liu; Wen-Quan He; Yung-Ming Chang; Yuan-Ho Chen) |
Abstract | In this paper, we present a hardware design which can support the inverse transform size from 32×32 in high efficiency video coding (HEVC) and is implemented by a using single 1-D IDCT core with a memory to low cost architecture. The proposed 1-D IDCT core employs two calculating paths to achieve a high throughput rate and is implemented by a 1-D inverse transform which can calculate 1st-D and 2nd-Ddata simultaneously in two parallel paths. The proposed 2-D transform core can implement a throughput rate of 332-Mpels/s with 129k gate area. |
Starting Page | 221 |
Ending Page | 224 |
File Size | 120394 |
Page Count | 4 |
File Format | |
e-ISBN | 9781479948086 |
DOI | 10.1109/ICIST.2014.6920370 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2014-04-26 |
Publisher Place | China |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Video coding Inverse discrete cosine transform (IDCT) Laplace equations High Efficiency Video Coding (HEVC) Computer architecture Logic gates Throughput Discrete cosine transforms Integer DCT |
Content Type | Text |
Resource Type | Article |
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