NDLI: Low-swing interconnect interface circuits

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2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

International Symposium on Low Power Electronics and Design (ISLPED)

IEEE/ACM International Symposium on Low Power Electronics and Design

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED)

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.

Proceedings of the International Symposium on Low Power Electronics and Design

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581)

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)

Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379)

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379)

Table of contents

High performance DSPs-what's hot and what's not?

Low power and low voltage CMOS digital circuit techniques

CMOS front end components for micropower RF wireless systems

A 1.4-GHz 3-mW CMOS LC low phase noise VCO using tapped bond wire inductances

A 3.8-mW 2.5-GHz dual-modulus prescaler in a 0.8 /spl mu/m silicon bipolar production technology

Towards the capability of providing power-area-delay trade-off at the register transfer level

Stream synthesis for efficient power simulation based on spectral transforms [CMOS logic]

Theoretical bounds for switching activity analysis in finite-state machines

Low power salient integration mode image sensor with a low voltage mixed-signal readout architecture

A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSls

3D CMOS SOI for high performance computing

A high speed and low power SOI inverter using active body-bias

Power and performance tradeoffs using various caching strategies

Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors

The simulation and evaluation of dynamic voltage scaling algorithms

Optimizing the DRAM refresh count for merged DRAM/logic LSIs

Integrated DC/DC converter with digital controller

CMOS VCOs for frequency synthesis in wireless biotelemetry

The impact of data characteristics and hardware topology on hardware selection for low power DSP

Low threshold CMOS circuits with low standby current

Minimum supply voltage for bulk Si CMOS GSI

0.5 V CMOS logic delivering 200 million 8/spl times/8 bit multiplications/s at less than 100 fJ based on a 50 nm T-gate SOI technology

Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits

Power-delay tradeoffs for radix-4 and radix-8 dividers

Automatic characterization and modeling of power consumption in static RAMs

Improving sampling efficiency for system level power estimation

Power invariant vector compaction based on bit clustering and temporal partitioning

An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors

Power calculation and modeling in deep submicron

Partial bus-invert coding for power optimization of system level bus

The Petrol approach to high-level power estimation

Power consumption of parallel spread spectrum correlator architectures

A low power video processor

Power dissipated by CMOS gates driving lossless transmission lines

Emerging power management tools for processor design

Recent developments in high integration multi-standard CMOS transceivers for personal communication systems

Low-energy embedded FPGA structures

Low-swing interconnect interface circuits

True single-phase energy-recovering logic for low-power, high-speed VLSI

System-level power estimation and optimization

Memory modeling for system synthesis

Monitoring system activity for OS-directed dynamic power management

A reconfigurable dual output low power digital PWM power converter

Voltage scheduling problem for dynamically variable voltage processors

On the optimum design of regulated cascode operational transconductance amplifiers

Low power logic synthesis under a general delay model

Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction

A power optimization method considering glitch reduction by gate sizing

A unified approach in the analysis of latches and flip-flops for low-power systems

Estimation of maximum power supply noise for deep sub-micron designs

Estimation of standby leakage power in CMOS circuit considering accurate modeling of transistor stacks

Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits

Decorrelating (DECOR) transformations for low-power adaptive filters

The logarithmic number system for strength reduction in adaptive filtering

Low power architecture of the soft-output Viterbi algorithm

Low power methodology and design techniques for processor design

Power distribution in high-performance design

Low-power miniaturized information display systems

Low-power embedded SRAM macros with current-mode read/write operations

A three-port adiabatic register file suitable for embedded applications

A low power SRAM using auto-backgate-controlled MT-CMOS

Fast high-level power estimation for control-flow intensive designs

The energy complexity of register files

Power exploration for dynamic data types through virtual memory management refinement

Proceedings of 1997 International Symposium on Low Power Electronics and Design

Proceedings of 1996 International Symposium on Low Power Electronics and Design

Low-swing interconnect interface circuits

Content Provider	IEEE Xplore Digital Library
Author	Hui Zhang Rabaey, J.
Copyright Year	1998
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA (Hui Zhang)
Abstract	This paper reviews a number of low-swing on-chip interconnect schemes, and presents a thorough analysis of their effectiveness and limitations. In addition, several new interface circuits, presenting even more energy savings, are proposed. Some of these circuits not only reduce the interconnect swing, but also use very-low supply voltages, so as to obtain quadratic energy savings. The performance of each of the presented circuits is thoroughly examined using simulation on a benchmark interconnect circuit. Energy savings with a factor of seven have been observed for some of the schemes.
Starting Page	161
Ending Page	166
File Size	644323
Page Count	6
File Format	PDF
ISBN	1581130597
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-08-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Integrated circuit interconnections Wires Circuit testing Driver circuits Energy consumption Inverters Voltage Circuit simulation Clocks Permission
Content Type	Text
Resource Type	Article

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