NDLI: Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)

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Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)

Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)

Low power RF integrated circuits: principles and practice

Algorithm and architecture of a 1 V low power hearing instrument DSP

A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells

Retractile clock-powered logic

Energy-efficient dynamic circuit design in the presence of crosstalk noise

Energy-efficient signal processing via algorithmic noise-tolerance

Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage

A low energy architecture for fast PN acquisition

Vibration-to-electric energy conversion

Variable supply-voltage scheme with 95%-efficiency DC-DC converter for MPEG-4 codec

Circuit methods for the integration of low voltage (1.1-1.8 V) analog functions on system-on-a-chip ICs in single-poly CMOS processes

Using dynamic cache management techniques to reduce energy in a high-performance processor

Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation

Energy efficient data transfer and storage organization for a MAP turbo decoder module

Mixed-swing quadrail for low power dual-rail domino logic

Databus charge recovery: practical considerations

SC/sup 2/L; a low-power high-performance dynamic differential logic family

Conforming inverted data store for low power memory

Ultra-low power digital subthreshold logic circuits

Single-phase source-coupled adiabatic logic

Global register allocation for minimizing energy consumption

Power macro-models for DSP blocks with application to high-level synthesis

Power minimization of high-performance submicron CMOS circuits using a dual-V/sub dd/ dual-V/sub th/ (DVDV) approach

A completely on-chip voltage regulation technique for low power digital circuits

Comparison of class A amplifiers for low-power and low-voltage switched capacitor applications

Lower and upper bounds an the switching activity in scheduled data flow graphs

Energy-per-cycle estimation at RTL

Efficient switching activity computation during high-level synthesis of control-dominated designs

Non-stationary effects in trace-driven power analysis

Low power synthesis of dual threshold voltage CMOS VLSI circuits

Clock distribution using multiple voltages

Monotonic static CMOS and dual V/sub T/ technology

VIP-an input pattern generator for identifying critical voltage drop for deep sub-micron designs

Technology and design challenges for low power and high performance [microprocessors]

Power scalable processing using distributed arithmetic

Challenges in clockgating for a low power ASIC methodology

Modeling and automating selection of guarding techniques for datapath elements

The design of a low energy FPGA

Stochastic modeling of a power-managed system: construction and optimization

The impact of battery capacity and memory bandwidth on CPU speed-setting: a case study

Selective instruction compression for memory energy reduction in embedded systems

Energy-efficient design of battery-powered embedded systems

A physical alpha-power law MOSFET model

Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits

Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation

A 1.2 V, 430 MHz, 4 dBm power amplifier and a 25 /spl mu/W front-end, using a standard digital CMOS process

CMOS front-end LNA-mixer for micropower RF wireless systems

Differential PLL for wireless applications using differential CMOS LC-VCO and differential charge pump

Passive precharge and rippled power logic (PPRPL)

Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's

An architectural solution for the inductive noise problem due to clock-gating

An optimization technique for dual-output domino logic

Statistically optimized asynchronous barrel shifters for variable length codecs

Inverse polarity techniques for high-speed/low-power multipliers

Instruction fetch energy reduction using loop caches for embedded applications with small tight loops

A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints

Way-predicting set-associative cache for high performance and low energy consumption

Designing power efficient hypermedia processors

Dynamic power estimation using the probabilistic contribution measure (PCM)

Circuit styles and strategies for CMOS VLSI design on SOI

System-level power optimization: techniques and tools

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