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Content Provider | IEEE Xplore Digital Library |
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Author | Dayu Wang Xiaoping Cui Xiaojing Wang |
Copyright Year | 2011 |
Description | Author affiliation: College of Electronics and Information Engineering, Nanjing, University of Aeronautics and Astronautics; Nanjing China (Dayu Wang; Xiaoping Cui; Xiaojing Wang) |
Abstract | Parallel-prefix computation provides a highly efficient solution to binary addition problem. This paper proposes an advanced design based on parallel-prefix Ling adder. In order to further improve the Ling adder's performance, the preprocessing block and carry propagation block are all optimized to reduce the delay path for sum generation. Experimental results indicate that the proposed adder has an improvement of 21 percent time delay and 25 percent area compared to the traditional Ling adders. |
Starting Page | 941 |
Ending Page | 944 |
File Size | 233963 |
Page Count | 4 |
File Format | |
ISBN | 9781457703201 |
e-ISBN | 9781457703218 |
DOI | 10.1109/ICECC.2011.6066361 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2011-09-09 |
Publisher Place | China |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Ling adder Logic gates Very large scale integration Educational institutions VLSI design Mathematical model Logic optimization Parallel-prefix algorithm Adders Delay Equations |
Content Type | Text |
Resource Type | Article |
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