NDLI: High rate (3, k) regular LDPC encoder architecture

Content Provider	IEEE Xplore Digital Library
Author	Anggraeni, S. Hussin, F.A. Jeoti, V.
Copyright Year	2011
Description	Author affiliation: Electrical and Electronics Engineering Department, Universiti Teknologi PETRONAS, Bandar Seri Iskandar, 31750 Tronoh, Perak, Malaysia (Anggraeni, S.; Hussin, F.A.; Jeoti, V.)
Abstract	This paper highlights recent developments in low density parity check (LDPC) encoder. There are some parameters applied in LDPC encoder such as type of LDPC codes, code length, code rate and encoding method. We emphasize that no attempts have been made for the implementation of (3, k) regular LDPC encoder with high code rate (R ≥ 0.875) and few works on flexible LDPC encoder which accommodates various code rates and code lengths. Therefore, this paper proposes a high rate (3, k) regular LDPC encoder architecture which is suitable for high code rate (R ≥ 0.875) applications. Division of workloads between stages is built based on the number of non-zero elements in the parity check matrix (H).
Starting Page	1
Ending Page	6
File Size	540771
Page Count	6
File Format	PDF
ISBN	9781457718823
e-ISBN	9781457718847
DOI	10.1109/NatPC.2011.6136390
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-19
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Low density parity check (LDPC) Bit error rate Encoder Computer architecture Parity check codes Complexity theory Field programmable gate array (FPGA) Channel coding Field programmable gate arrays Encoding complexity Code rate
Content Type	Text
Resource Type	Article

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