NDLI: Design and implementation of LDPC(Low Density Parity Check) coding technique on FPGA (Field Programmable Gate Array) for DVB-S2 (Digital Video Broadcasting-Satellite)

Content Provider	IEEE Xplore Digital Library
Author	Purnamasari, Rita Wijanto, Heroe Hidayat, Iswahyudi
Copyright Year	2014
Description	Author affiliation: Electrical Engineering Faculty, Telkom University, Jl. Telekomunikasi, Dayeuh Kolot, Bandung 40257 Telp., Indonesia (Purnamasari, Rita; Wijanto, Heroe; Hidayat, Iswahyudi)
Abstract	LDPC (Low Density Parity Check) is a channel coding technique is used to correct errors so that the validity of a data transmission on the noise transmission channel guaranteed for accuracy. LDPC is suitable for applications that require a large bandwidth, high reliability, and high noise channel like DVB-S2 (Digital Video Broadcast-Satellite) application. Despite the high level of complexity, LDPC coding technique is very possible to be implemented in line with the growing hardware capabilities. The purpose of this research later is to make DVB-S2 chips that can transmit digital video via satellite.
Starting Page	83
Ending Page	88
File Size	708650
Page Count	6
File Format	PDF
e-ISBN	9781479961887
DOI	10.1109/ICARES.2014.7024407
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-13
Publisher Place	Indonesia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bit flipping FPGA(Field Programmable Gate Array) Virtex-4 Parity check codes Encoding Decoding Lower triangular Mathematical model LDPC(Low Density Parity Check) Field programmable gate arrays Digital video broadcasting Clocks DVB-S (Digital)
Content Type	Text
Resource Type	Article

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