NDLI: Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments

Content Provider	IEEE Xplore Digital Library
Author	Bekiaris, D. Sotiriou-Xanthopoulos, E. Economakos, G. Soudris, D.
Copyright Year	2012
Description	Author affiliation: National Technical University of Athens, School of Electrical and Computer Engineering, Microprocessors and Digital Systems Laboratory, Heroon Polytechniou 9, GR-15780 Zografou, Athens, Greece (Bekiaris, D.; Sotiriou-Xanthopoulos, E.; Economakos, G.; Soudris, D.)
Abstract	Modern digital design has been greatly forced to offer More-Moore integration densities and very high operation frequencies for demanding applications. In this search-for-performance race, alternative and less radical More-than-Moore solutions are emerging, like reconfigurable computing. Reconfigurable computing stands between hardware and software and promises to offer the former's performance alongside with the latter's flexibility. Research in the field deals with fine or coarse grain reconfigurable components and efficient ways to map applications onto them. In this paper, a systematic design methodology and evaluation of a coarse grain reconfigurable component targeting the ASIC domain is presented. The specific component is a morphable architecture, that works in mutually exclusive modes, offering different functionality in each mode. The novelty presented in this paper is a systematic evaluation of the scalability of the morphable component. Continuously functionally improved modes are evaluated for performance, area and power, in order to choose the best architecture for a number of widely used DSP applications. Overall, a $power^{∗}$ performance improvement of up to 24% is reported and a $power^{∗}$ area of up to 13% compared to conventional, non-reconfigurable component architectures.
Starting Page	1
Ending Page	8
File Size	312510
Page Count	8
File Format	PDF
ISBN	9781467325707
e-ISBN	9781467325721
e-ISBN	9781467325714
DOI	10.1109/ReCoSoC.2012.6322890
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-07-09
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing Reconfigurable multiplier Design methodologies Runtime reconfiguration Microprocessors High-level synthesis Computer architecture Reconfigurable computing Hardware Timing Adders Optimization
Content Type	Text
Resource Type	Article

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