NDLI: 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)

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2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)

Automated composition and execution of hardware-accelerated operator graphs

Automated minimization of concurrent online checkers for Network-on-Chips

Configurable cache tuning with a victim cache

A decentralised, autonomous, and congestion-aware thermal monitoring infrastructure for photonic network-on-chip

On the design of highly reliable system-on-chip using dynamically reconfigurable FPGAs

Emulation of an ASIC power and temperature monitor system for FPGA prototyping

An energy-aware scheduler for dynamically reconfigurable multi-core systems

Energy efficient 3D Hybrid processor-memory architecture for the dark silicon age

Execution modeling in self-aware FPGA-based architectures for efficient resource management

Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs

A flexible co-processing approach for SoC-FPGAs based on dynamic partial reconfiguration and bitstream relocation methods

FPGA based traffic sign detection for automotive camera systems

A framework for hardware-based DVFS management in multicore mixed-criticality systems

A framework for remote and adaptive partial reconfiguration of SoC based data acquisition systems under Linux

Hardware-accelerated Response Time Analysis for priority-preemptive Networks-on-Chip

Hybrid FPGA approach for a $B^{+}$ tree in a Semantic Web database system

Mixed-criticality NoC partitioning based on the NoCDepend dependability technique

A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications

Predictable photonic interconnects using an autonomous channel management and a TDMA-NoC

Reconfigurable communication fabric for efficient implementation of neural networks

Reconfigurable security architecture for disrupted protection zones in NoC-based MPSoCs

Reconfigurable Vector Extensions inside the DRAM

S2AP: An efficient numerical-based crosstalk avoidance code for reliable data transfer of NoCs

Envisioning self-verification of electronic systems

A survey on security features in modern FPGAs

Towards cognitive reconfigurable hardware: Self-aware learning in RTR fault-tolerant SoCs

Using hardware parallelism for reducing power consumption in video streaming applications

Using the reconfigurability of modern FPGAs for highly efficient PUF-based key generation

Towards run-time flexible risk management systems on hybrid platforms

Design to survive

Beyond many-core: Commercial workload acceleration in high-end systems

Message from the chairs

ReCoSoC 2015 technical program

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

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Indian Institute of Technology Kharagpur
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03222 282435
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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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