NDLI: Lead-free solder paste selection and solder joint reliability for copper stud flip chip

Content Provider	IEEE Xplore Digital Library
Author	Fon Bih Wen Krishnan, S. Yo Meng Chan
Copyright Year	2008
Description	Author affiliation: ON Semicond., SCG Ind. Malaysia Sdn Bhd, Seremban (Fon Bih Wen; Krishnan, S.; Yo Meng Chan)
Abstract	With the escalating global gold (Au) price, most of the semiconductor manufacturers swiftly convert from gold wire bonding to the Copper (Cu) wire bonding. Cu stud flip chip becomes a competitive option not only from the cost perspective; it aligns well with the miniaturization trend. Only minor modifications on the existing wire bond platform enables the tremendous cost saving on the material and reduces the hassles in stitch bonding. [1] However, solder joint reliability is a major concern in Cu stud flip chip package. The assembly process and the solder paste selection are critical in defining the robustness of the package. Hence, in this paper, we discussed the Cu stud bumping and exploration of different solder deposition methods. These include solder printing, solder dispensing and solder dipping process. Solder dipping is an alternative to the conventional solder deposition process as it offers lower cost and shorter process cycle time. The compatibility of the solder paste with the Ag spot Cu lead frame and the Cu stud is crucial in selecting a solder paste material. For this reason, SAC 305 solder paste was selected. Choosing the right lead-free solder paste includes selecting the compatible flux system. Flux residue, which often degrades the adhesion strength of the mold compound, needs to be minimized to reduce the delamination risk. Both type 5 and type 6 solder paste were evaluated for 0.2mm dot deposition at 0.5mm lead pitch. The reflow conditions for this small powder size SAC alloy were included in this paper. The assembled Cu stud flip chip packages were subjected to temperature cycle test to check on the integrity of the solder joint formed. Cross-sectioned units were observed under the high power scope. The paper also discussed the intermetallic growth at the solder joint after temperature cycling. The results showed that the Cu stud co-planarity and bump strength affects the joint reliability. Sufficient solder deposition was essential to ensure the Cu stud in contact with the solder paste and lead frame. Type 6 solder paste needed extra care during handling and reflowing to avoid failure in the solder joint formation. Cu-Sn intermetallic growth and Kirkendall void were observed after thermal aging. However, the electrical test result showed no significant shift in the resistance after thermal shock test.
Starting Page	80
Ending Page	83
File Size	3338988
Page Count	4
File Format	PDF
ISBN	9781424436200
DOI	10.1109/EMAP.2008.4784234
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-22
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Environmentally friendly manufacturing techniques Lead Soldering Copper Flip chip Bonding Gold Wire Costs Packaging
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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