NDLI: C4NP - Lead Free Flip Chip Solder Bumping Manufacturing and Reliability Data

Content Provider	IEEE Xplore Digital Library
Author	Laine, E. Ruhmer, K. Belanger, L. Turgeon, M. Perfecto, E. Longworth, H. Hawken, D.
Copyright Year	2006
Description	Author affiliation: SUSS MicroTec, Inc., Waterbury, VT (Laine, E.; Ruhmer, K.)
Abstract	To meet future requirements for cost, size, weight and electrical performance, microelectronic packaging is moving from wire bonds to solder bumps as the preferred method of interconnection from the device to the chip carrier or card. Flip chip in package (FCiP) requires many small bumps on tight pitch whereas wafer level chip scale packaging (WLCSP) typically requires much larger solder bumps on a greater pitch. Electroplating, solder paste printing and the direct attach of preformed solder spheres are technologies commonly used in volume production for wafer bumping. Each of these techniques has limitations in scaling from fine pitch FCiP to WLCSP. Electroplating is better suited to fine pitch, whereas solder paste printing and solder sphere attachment work well for coarser pitches. C4NP (controlled collapse chip connection new process) has proven to be suitable for this entire range of solder bump pitch. C4NP is a new solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch FCiP as well as WLCSP bumping applications. This paper summarizes the latest manufacturing and reliability data for high-end logic device packaging using 300mm wafers bumped with C4NP. This includes initial reliability data for C4NP lead free solder bumped devices attached to organic chip carriers. Mold fill data for CSP type dimensions is included. Solder metrology data and yield information for fine pitch applications is summarized. Relevant process equipment technology and the unique requirements to run a high volume manufacturing C4NP process are reviewed. The paper also summarizes the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques. The data in this paper is provided by IBM's packaging operations at the Hudson Valley Research Park in East Fishkill, NY and Bromont, Quebec
Starting Page	1
Ending Page	8
File Size	7937113
Page Count	8
File Format	PDF
ISBN	1424406196
DOI	10.1109/ICEPT.2006.359758
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-08-26
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Environmentally friendly manufacturing techniques Lead Flip chip Costs Chip scale packaging Printing Wafer scale integration Pulp manufacturing Packaging machines Microelectronics
Content Type	Text
Resource Type	Article

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