NDLI: Compacting output responses containing unknowns using an embedded processor

Content Provider	IEEE Xplore Digital Library
Author	Saleem, K. Muthyala, S.S. Touba, N.A.
Copyright Year	2015
Description	Author affiliation: Comput. Eng. Res. Center, Univ. of Texas, Austin, TX, USA (Saleem, K.; Muthyala, S.S.; Touba, N.A.)
Abstract	In system-on-chip (SOC) designs, embedded processors are frequently present as part of the functional design and can be used to help test the chip or system by providing a software-based test. Previous work has looked at compacting output responses in software by performing signature analysis using either arithmetic operations or by implementing a multi-input signature register (MISR) in software. However, these approaches cannot be used when the output response contains unknown (X) values. While it is possible to precisely mask all X's present in the output response in software, a straightforward approach would require a very large amount of mask data to specify which bits to mask. This paper proposes an efficient method for compacting output responses with X's in software using the concept of canceling X's from signatures as proposed in [Touba 07], Whereas the efficiency of the hardware implementation in [Touba 07] is constrained by needing to minimize the hardware overhead, in software these constraints are not present. Thus, a novel and more efficient implementation is proposed here. Moreover, the efficiency is further improved by incorporating a low cost partial X-masking step in software as well. Results indicate that output responses with significant X densities can be very efficiently compacted using the proposed software-based scheme.
Starting Page	155
Ending Page	160
File Size	2913484
Page Count	6
File Format	PDF
e-ISBN	9781479986064
DOI	10.1109/DFT.2015.7315154
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-10-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decision support systems Fault tolerance Fault tolerant systems Very large scale integration Nanotechnology Discrete Fourier transforms Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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