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Content Provider | IEEE Xplore Digital Library |
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Author | Ishikawa, M. Edahiro, M. Yoshimura, T. Miyazaki, T. Aikoh, S.-I. Nishitani, T. Mitsuhashi, K. Furuichi, M. |
Copyright Year | 1990 |
Description | Author affiliation: NEC Corp., Kawasaki, Japan (Ishikawa, M.; Edahiro, M.; Yoshimura, T.; Miyazaki, T.; Aikoh, S.-I.; Nishitani, T.; Mitsuhashi, K.; Furuichi, M.) |
Abstract | A silicon compiler for finite impulse response (FIR) filters is presented. The synthesis system takes as inputs only filter specifications and processing word lengths, and generates the FIR filter mask patterns in a few minutes. The system consists of two programs: an FIR filter design program to determine FIR filter coefficients at the minimal filter order to meet design objectives, and a module generator to generate mask patterns according to optimal parameters obtained by the filter design program. For describing layout structures correctly and easily, the module generator provides graphical layout description tools, and includes mechanisms to permit designing the structures before leaf-cells are completed. Layouts for several filters which have been successfully generated in a short time are described. A system-generated single-chip VLSI chrominance-luminance separator for NTSC composite TV signals using four FIR filters is shown.< |
Starting Page | 2588 |
Ending Page | 2591 |
File Size | 503813 |
Page Count | 4 |
File Format | |
DOI | 10.1109/ISCAS.1990.112538 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 1990-05-01 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Finite impulse response filter Silicon compiler Band pass filters Very large scale integration Process design Signal design Algorithm design and analysis Digital signal processing chips Signal synthesis Layout |
Content Type | Text |
Resource Type | Article |
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