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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yang, M.M. Barby, J.A. |
| Copyright Year | 2004 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada (Yang, M.M.; Barby, J.A.) |
| Abstract | A novel fast true single phase clocking (TSPC) adiabatic differential logic circuit using dynamic threshold (DTMOS) is proposed (DT-TSPC-A). It is capable of operating at 0.7 V. The performance of four circuit architectures (DT-TSPC-A, conventional static CMOS logic, and two other published adiabatic circuits) is compared using a four inverter chain as the test circuit. At 50 MHz and 0.8 V with 20 fF load, this circuit consumes the least amount of energy of the four circuit architectures compared. It takes about the same area and consumes 55% less energy than the static circuit. It has the shortest delay and is 56% faster than other adiabatic circuits and takes at most 2.3 times the area. In addition results for more complex circuits are supplied demonstrating the improved performance of DT-TSPC-A circuits. |
| Sponsorship | IEEE Circuits and Syst. Soc |
| File Size | 238920 |
| File Format | |
| ISBN | 078038251X |
| DOI | 10.1109/ISCAS.2004.1329265 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-05-23 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Low voltage Clocks Logic circuits CMOS logic circuits Delay Energy consumption MOS devices Logic testing Inverters Circuit testing |
| Content Type | Text |
| Resource Type | Article |
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