NDLI: Implementation of low-voltage true-single-phase-clocking (TSPC) logic using bulk dynamic threshold MOS technique

Content Provider	IEEE Xplore Digital Library
Author	Ke Wu Song Jia Zhongjian Chen Xuewen Gan
Copyright Year	2005
Description	Author affiliation: Inst. of Microelectron., Peking Univ., Beijing (Ke Wu; Song Jia; Zhongjian Chen; Xuewen Gan)
Abstract	Dynamic threshold MOS circuits can adjust devices' threshold according to the states of the circuits and thus offer higher speed and better saving of energy at low voltage. In this paper a new fast bulk true single phase clocking (TSPC) dynamic threshold MOS scheme for both NMOS and PMOS is introduced. In this scheme the common substrate of the NMOS logic or PMOS logic is dynamically controlled: the potential changes only when these transistors need to work and keeps high threshold when they are shut down. And the scheme uses the charge recovery technique of the substrate, to further reduce power. It is capable of operating at 0.8V or even lower. The proposed scheme is shown to be 33.45% faster and has 20.86% energy savings compared to the regular TSPC logic circuits, during HSPICE simulation
Starting Page	158
Ending Page	162
File Size	533880
Page Count	5
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611287
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Threshold voltage MOS devices Clocks Logic devices Logic circuits Low voltage Circuit simulation Energy efficiency Dynamic voltage scaling
Content Type	Text
Resource Type	Article

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