NDLI: An optimized hardware architecture for intra prediction in H.264 decoder

Content Provider	IEEE Xplore Digital Library
Author	Qi Wang Quanquan Li Shi Chen Tiejun Zhang Chaohuan Hou
Copyright Year	2013
Description	Author affiliation: Digital Syst. Integration Lab., Inst. of Acoust., Beijing, China (Qi Wang; Quanquan Li; Shi Chen; Tiejun Zhang; Chaohuan Hou)
Abstract	The advanced video coding standard H.264 is widely used to compress video data for applications such as Digital Still Camera (DSC), Digital Video Camera (DVC), Television Studio Broadcast, and Surveillance Video. Intra prediction is one of the most critical issues in H.264 decoding in terms of processing cycles and computation complexity, it is the system bottleneck of real-time H.264 decoding. This paper presents an area optimized memory update mechanism. For luma 4×4 block prediction, the proposed architecture only adds four registers to store the corner pixels based on luma 16×16 block prediction. A high efficient 4×4 block level pipeline is also presented in this paper. The pipelined architecture eliminates data dependencies between two neighboring blocks thoroughly by inserting chroma 4×4 block processing into luma 4×4 block processing. The proposed architecture is verified to work at 160MHz in a Xilinx Virtex-II pro FPGA. It costs about 23k gates by using SIMC 90nm technology and supports real-time decoding with 1080p format video in 30fps.
Sponsorship	IEEE Beijing Sect.
Starting Page	1
Ending Page	4
File Size	812263
Page Count	4
File Format	PDF
ISBN	9781467364157
ISSN	2162755X
e-ISBN	9781467364171
DOI	10.1109/ASICON.2013.6811847
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-28
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Random access memory Computer architecture Registers Pipelines Hardware Streaming media Intra prediction H.264 decoder
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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