NDLI: SoPC Self-Integration Mechanism for Seamless Architecture Adaptation to Stream Workload Variations

Content Provider	IEEE Xplore Digital Library
Author	Dumitriu, V. Kirischian, L.
Copyright Year	1993
Abstract	Field-programmable gate arrays are becoming one of the implementation platforms of choice for computationally intensive embedded applications, such as multimode stream processors; such systems often exhibit poor cost-efficiency as various system modules can be idle, based on operating mode. This problem can be addressed through the use of reconfigurable computing, which allows underlying logic resources to be shared among system modules; using this approach, an application and mode specific processor can be generated at run-time. However, this generation process can interfere with application workloads; this is particularly true in the case of high data-rate stream processors. To address this problem, this brief presents a system-on-programmable-chip self-integration mechanism aimed at reconfigurable stream processors. The proposed mechanism is implemented using a distributed architecture and the multimode adaptive collaborative reconfigurable self-organized system framework. The mechanism arranges configuration, link establishment, and scheduling tasks around the stream workload, which allows for seamless run-time architecture adaptation. When compared with traditional approaches, based on central, instruction-based sequential processors, the proposed approach is shown to offer a faster (up to 10 times) link establishment and the scheduling capabilities; more importantly, the proposed mechanism can offer seamless run-time architecture adaptation by allowing the overlap of processing and configuration tasks.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	799
Ending Page	802
Page Count	4
File Size	919092
File Format	PDF
ISSN	10638210
Volume Number	24
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2016-01-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Computer architecture Field programmable gate arrays System-on-chip Real-time systems Streaming media Engines system-on-chip (SoC). Field programmable gate arrays (FPGAs) pipeline processing reconfigurable architectures system-on-chip (SoC)
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Software Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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