NDLI: Conference proceedings FPL 2015

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2015 25th International Conference on Field Programmable Logic and Applications (FPL)

Significant papers from the first 25 years of the FPL conference

Conference proceedings FPL 2015

Efficient assembly for high order unstructured FEM meshes

A scalable FPGA architecture for nonnegative least squares problems

Towards heterogeneous solvers for large-scale linear systems

A software configurable coprocessor-based state-space controller

A deep convolutional neural network based on nested residue number system

Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference

A scalable pipelined architecture for biomimetic vision sensors

FPGA implementation to estimate the number of endmembers in hyperspectral images

Power-efficient range-match-based packet classification on FPGA

A variable length hash method for faster short read mapping on FPGA

Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform

From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis

A study of data partitioning on OpenCL-based FPGAs

Limits of FPGA acceleration of 3D Green's Function computation for geophysical applications

Recursive pipelined genetic propagation for bilevel optimisation

Automatic generation of high throughput energy efficient streaming architectures for arbitrary fixed permutations

Using island-style bi-directional intra-CLB routing in low-power FPGAs

Energy optimization of FPGA-based stream-oriented computing with power gating

Energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs

Compact dual block AES core on FPGA for CCM Protocol

Towards efficient discrete Gaussian sampling for lattice-based cryptography

An efficient many-core architecture for Elliptic Curve Cryptography security assessment

High speed ECC implementation on FPGA over $GF(2^{m})$

A fully pipelined kernel normalised least mean squares processor for accelerated parameter optimisation

An efficient reconfigurable architecture by characterizing most frequent logic functions

Static hardware task placement on multi-context FPGA using hybrid genetic algorithm

Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow

Hoplite: Building austere overlay NoCs for FPGAs

Variable-latency signed addition on FPGAs

Inter-procedural resource sharing in High Level Synthesis through function proxies

SysAlloc: A hardware manager for dynamic memory allocation in heterogeneous systems

Efficient data-stream management for shared-memory many-core systems

A scalable architecture for multi-class visual object detection

Enhancing stochastic computations via process variation

$AmBRAM^{s}$ - An analysis tool, method and framework for advanced measurements and reliability assessments on modern nanoscale FPGAs

7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2

Design and simulation tools for Embedded NOCs on FPGAs

NetFPGA - rapid prototyping of high bandwidth devices in open source

Building a distributed key-value store with FPGA-based microservers

High-level FPGA logic synthesis from .NET programs for software developers

Hierarchical library based power estimator for versatile FPGAs

FPGA-based all-digital software defined radio system demonstration

rrBox: A remote dynamically reconfigurable network processing middlebox

FPGA based nonlinear Support Vector Machine training using an ensemble learning

An FPGA implementation of a phylogenetic tree reconstruction algorithm using an alternative second-pass optimization

Ultra low latency dataflow renderer

Parallel feature extraction and heterogeneous object-detection for multi-camera driver assistance systems

A transport-layer network for distributed FPGA platforms

Generating FPGA accelerators for chemical similarity assessment

Data protection using recursive inverse function

Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs

An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs

Pipelined NoC router architecture design with buffer configuration exploration on FPGA

Accurate power analysis for near-V RRAM-based FPGA

OpenCL computing on FPGA using multiported

Adaptive MRAM-based CGRAs

Reduction calculator in an FPGA based switching Hub for high performance clusters

Serial and parallel interleaved modular multipliers on FPGA platform

A framework for integrated monitoring of real-time embedded SoC

Greedy approach based heuristics for partitioning SpMxV on FPGAs

Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip

Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems

Towards a guided design flow for heterogeneous reconfigurable architectures

High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAs

FPGA-based all-digital Software Defined Radio receiver

Over effective hard real-time hardware tasks scheduling and allocation

FPGA-based all-digital transmitters

A run time interpretation approach for creating custom accelerators

Data-triggered breakpoint for in-circuit debug without re-implementation

Characterisation of feasibility regions in FPGAs under adaptive DVFS

A resilient, flash-free soft error mitigation concept for the CBM-ToF read-out chain via GBT-SCA

UniStream: A unified stream architecture combining configuration and data processing

Placing partially reconfigurable stream processing applications on FPGAs

A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs

In-field vulnerability analysis of hardware-accelerated computer vision applications

A rapid prototyping framework for nano-photonic accelerators

Fast FPGA system for microarchitecture optimization on synthesizable modern processor design

An LZ77-style bit-level compression for trace data compaction

Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry

Wotan: A tool for rapid evaluation of FPGA architecture routability without benchmarks

Temperature-triggered behavioral IPs HW Trojan detection method with FPGAs

Estimating circuit delays in FPGAs after technology mapping

Automatic support for multi-module parallelism from computational patterns

ParaLaR: A parallel FPGA router based on Lagrangian relaxation

Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs

A technology mapper for depth-constrained FPGA logic cells

SPINE: From C loop-nests to highly efficient accelerators using Algorithmic Species

Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices

CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing

Scavenger: Automating the construction of application-optimized memory hierarchies

Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators

Software-in-the-Loop simulation of embedded control applications based on Virtual Platforms

Ultra-fast NoC emulation on a single FPGA

Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions

Hybrid FPGA debug approach

PushPush: Seamless integration of hardware and software objects via function calls over AXI

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

2013 23rd International Conference on Field programmable Logic and Applications

22nd International Conference on Field Programmable Logic and Applications (FPL)

2011 21st International Conference on Field Programmable Logic and Applications

2010 International Conference on Field Programmable Logic and Applications

2009 International Conference on Field Programmable Logic and Applications

2008 International Conference on Field Programmable Logic and Applications

2007 International Conference on Field Programmable Logic and Applications

2006 International Conference on Field Programmable Logic and Applications

International Conference on Field Programmable Logic and Applications, 2005.

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