NDLI: Non-Manhattan routing using a Manhattan router

Content Provider	IEEE Xplore Digital Library
Author	Hursey, E. Jayakumar, N. Khatri, S.P.
Copyright Year	2005
Description	Author affiliation: Dept. of ECE, Colorado Univ., Boulder, CO, USA (Hursey, E.)
Abstract	In deep sub-micron (DSM) designs, wire delays comprise a significant fraction of the total delay of a design. Therefore, techniques such as non-Manhattan routing, which reduce the total wire length of a design, are highly relevant for today's designs. However, a great deal of effort has gone into the design and development of algorithms to perform Manhattan routing, both in industry and in academia. Therefore, it would be desirable to use existing Manhattan algorithms and tools to perform non-Manhattan routing. In this paper, we describe a technique to perform non-Manhattan routing by combining the results of two related Manhattan routing instances. The second routing instance is derived from the first by rotating the coordinate system by 45/spl deg/. As a result, the Manhattan routes that are computed for the second instance are actually 45 /spl deg/ rotated in the original coordinate system. We combine the results of the two instances to obtain a final routing result that contains non-Manhattan routes. We demonstrate that our router produces highly efficient results, reducing the total wire length by an average 9.8% over a traditional router, with a via-count increase of 2%.
Starting Page	445
Ending Page	450
File Size	103385
Page Count	6
File Format	PDF
ISBN	0769522645
ISSN	10639667
DOI	10.1109/ICVD.2005.124
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Wire Wiring Very large scale integration Pins Clocks Algorithm design and analysis Delay systems Counting circuits Research and development
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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