NDLI: Cooling and power considerations for semiconductors into the next century

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2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

International Symposium on Low Power Electronics and Design (ISLPED)

IEEE/ACM International Symposium on Low Power Electronics and Design

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED)

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.

Proceedings of the International Symposium on Low Power Electronics and Design

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581)

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581)

Wireless beyond the third generation-facing the energy challenge

Micro-operation cache: a power aware frontend for variable instruction length ISA

L1 data cache decomposition for energy efficiency

Instruction flow-based front-end throttling for power-aware high-performance processors

Energy reduction in queues and stacks by adaptive bitwidth compression

Energy priority scheduling for variable voltage processors

Dynamic voltage scheduling technique for low-power multimedia applications using buffers

Power-aware modulo scheduling for high-performance VLIW processors

Hard real-time scheduling for low-energy using stochastic data and DVS processors

Analysis and design of low-energy flip-flops

Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation

A low-power motion estimation block for low bit-rate wireless video

Power-aware partitioned cache architectures

A low-leakage dynamic multi-ported register file in 0.13 /spl mu/m CMOS

Energy-efficient load and store reuse

Compiler support for block buffering

Automatic source code specialization for energy reduction

FV encoding for low-power data I/O

Time-to-failure estimation for batteries in portable electronic systems

Architecture strategies for energy-efficient packet forwarding in wireless sensor networks

Modulation scaling for energy aware communication systems

Cooling and power considerations for semiconductors into the next century

Energy efficient modulation and MAC for asymmetric RF microsensor systems

A 1 V, 1.9 GHz mixer using a lateral bipolar transistor in CMOS

A 60dB, 246MHz CMOS variable gain amplifier for subsampling GSM receivers

VTCMOS characteristics and its optimum conditions predicted by a compact analytical model

Memory controller policies for DRAM power management

Run-time power estimation in high performance microprocessors

Fast, flexible, cycle-accurate energy estimation

Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors

Theory and practical implementation of harmonic resonant rail driver

Resonant clock generator for single-phase adiabatic systems

Enhanced multi-threshold (MTCMOS) circuits using variable well bias

Encodings for high-performance energy-efficient signaling

Low-energy encoding for deep-submicron address buses

Irredundant address bus encoding for low power

Low power address encoding using self-organizing lists

Wireless sensor networks: application driver for low power distributed systems

Scaling of stack effect and its application for leakage reduction

Variable threshold voltage CMOS (VTCMOS) in series connected circuits

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design

A self-optimizing embedded microprocessor using a loop table for low power

Low power pipelining of linear systems: A common operand centric approach

A system-level energy minimization approach using datapath width optimization

Energy-efficient instruction dispatch buffer design for superscalar processors

High density capacitance structures in submicron CMOS for low power RF applications

A CMOS VCO architecture suitable for sub-1 volt high-frequency (8.7-10 GHz) RF applications

Low-power direct-sequence spread-spectrum modem architecture for distributed wireless sensor networks

Effects of elevated temperature on tunable near-zero threshold CMOS

A sub-1V dual-threshold domino circuit using product-of-sum logic

Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design

Selectively clocked skewed logic (SCSL): a robust low-power logic style for high-performance applications

A profile-based energy-efficient intra-task voltage scheduling algorithm for hard real-time applications

Compiler-directed dynamic voltage/frequency scheduling for energy reduction in microprocessors

Variable voltage task scheduling algorithms for minimizing energy

Design methodology and optimization strategy for dual-V/sub TH/ scheme using commercially available tools

Synthesis of low-leakage PD-SOI circuits with body-biasing

Low-power technology mapping for mixed-swing logic

Frequency-domain supply current macro-model

A low-power, 5-70 MHz, 7th-order filter with programmable boost, group delay, and gain using instantaneous companding

Optimizing bias-circuit design of cascode operational amplifier for wide dynamic range operations

Leakage current cancellation technique for low power switched-capacitor circuits

A 3-pin 1.5 V 550 /spl mu/W 176 /spl times/ 144 self-clocked CMOS active pixel image sensor

Cached-code compression for energy minimization in embedded processors

Energy efficient turbo decoding for 3G mobile

Low-power AEC-based MIMO signal processing for Gigabit Ethernet 1000Base-T transceivers

Power reduction through work reuse [superscalar processor microarchitecture]

Clocking strategies and scannable latches for low power applications

Ultra-low power DLMS adaptive filter for hearing aid applications

A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU

Analysis and implementation of charge recycling for deep sub-micron buses

Estimation of power distribution in VLSI interconnects

Maximum voltage variation in the power distribution network of VLSI circuits with RLC models

Battery capacity measurement and analysis using lithium coin cell battery

On the interaction of power distribution network with substrate

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)

Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379)

Proceedings of 1997 International Symposium on Low Power Electronics and Design

Proceedings of 1996 International Symposium on Low Power Electronics and Design

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