NDLI: Design and Implementation of Various Topologies for Networks on Chip and Its Performance Evolution

Content Provider	IEEE Xplore Digital Library
Author	Gugulothu, S. Chawhan, M.D.
Copyright Year	2014
Description	Author affiliation: Dept. Electron.& Commun. Eng., RCOEM, Nagpur, India (Chawhan, M.D.) \|\| Dept. of Electron. Eng., YCCE, Nagpur, India (Gugulothu, S.)
Abstract	The density of integration in a single chip has progressed by use of the deep submicron of VLSI design rule. Systems on a chip (for short, SoCs), i.e., several functional cores being integrated in a single chip, have become the mainstream technology. On the other hand, A Network on a Chip (NoC), i.e., a communication-centric platform, offers an on-chip interconnection network. The NoC is one of the on-chip communication systems. The NoC is used in place of conventional shared bus systems. There are many NoC topologies for connecting cores to each other, such as Mesh, Ring, Spider on, and so on. To evaluate the NoC topologies, a simulation based approach was used for the modeling and analysis of the topologies. However, some properties of the topologies could affect the performance of the NoC systems. This paper describes about the performances of the topologies about the communication aspects by the simulation based approach.
Sponsorship	IEEE Bombay Sect.
Starting Page	7
Ending Page	11
File Size	950531
Page Count	5
File Format	PDF
ISBN	9781479921027
DOI	10.1109/ICESC.2014.10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-09
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Network topology Ports (Computers) Ring Computer architecture Routing Mesh Spidergon Topology System-on-chip Delays Network on Chip System on Chip
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Fault tolerant routing implementation mechanism for irregular 2D mesh NoCs

Use of irregular topologies for the synthesis of networks-on-chip

High-Throughput Compact Delay-Insensitive Asynchronous NoC Router

A novel hybrid topology for Network on Chip

Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh

An improved minimal multicast routing algorithm for mesh-based Networks-on-Chip

Design and evaluation of virtual channel router for mesh-of-grid based NoC

Area and power efficient network on chip router architecture

A Network on Chip Architecture and Performance Evaluation

Design and Implementation of Various Topologies for Networks on Chip and Its Performance Evolution

Similar Documents

Fault tolerant routing implementation mechanism for irregular 2D mesh NoCs

Use of irregular topologies for the synthesis of networks-on-chip

High-Throughput Compact Delay-Insensitive Asynchronous NoC Router

A novel hybrid topology for Network on Chip

Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh

An improved minimal multicast routing algorithm for mesh-based Networks-on-Chip

Design and evaluation of virtual channel router for mesh-of-grid based NoC

Area and power efficient network on chip router architecture

A Network on Chip Architecture and Performance Evaluation

Design and Implementation of Various Topologies for Networks on Chip and Its Performance Evolution