NDLI: An improved RC model for VLSI interconnects with applications to buffer insertion

Content Provider	SpringerLink
Author	Al Taee, Alaa R. Yuan, Fei Ye, Andy
Copyright Year	2013
Abstract	A general platform to generate the RC, RLC and RLCG models of interconnects using global approximation method, two-port networks, and asymptotic waveform evaluation (AWE) is presented. Using the delay of transmission-line-modeled interconnects from HSPICE as a bench mark, we show that among all 18 models studied, the π-configuration of AWE-RLC model yields the best accuracy. To reduce complexity subsequently computational cost without sacrificing accuracy, the AWE-RLC model is mapped to a complex RC model using moment matching. The complex RC model is further mapped to an improved RC model utilizing the principle of charge reservation. The improved RC model is employed to estimate the delay of long interconnects with buffer insertion. As compared with the conventional RC model, the improved RC model reduces the delay of interconnects with buffer insertion, the number of buffers, and the size of the buffer by 20.5, 24, and 32 %, respectively.
Starting Page	105
Ending Page	113
Page Count	9
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	79
Issue Number	1
e-ISSN	15731979
Language	English
Publisher	Springer US
Publisher Date	2013-09-24
Publisher Place	Boston
Access Restriction	Subscribed
Subject Keyword	On-chip interconnect Buffer insertion Global approximation method (GAM) Two-port networks (TPN) Asymptotic waveform evaluation (AWE) Circuits and Systems Electrical Engineering Signal, Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

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