NDLI: Run-Time Component Relocation in Partially-Reconfigurable FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Dumitriu, V. Marcantonio, D. Kirischian, L.
Copyright Year	2009
Abstract	The concept of hardware resource virtualization which was initiated in virtual memory organization has recentlyexpanded towards virtualization of computing resources inpartially reconfigurable FPGAs. However, this kind of resource virtualization requires mechanisms for flexible allocation/relocation of components associated with data execution processes. The ability for on-chip component relocation will allow costefficient multi-task/multi-modal operations in FPGAs by run-time architecture-to-task optimization. On-chip component relocation would also allow hardware fault mitigation and even dynamic self-restoration of FPGA systems. Therefore, the goal of the presented research was to investigate the feasibilityof on-chip component relocation in partially reconfigurableFPGAs. In this proof-of-concept research phase we haveanalyzed structural requirements of target FPGAs as well asdesign constraints for the components suitable for on-chiprelocation. As a result, the possibility for run-time relocation of components associated with video-processing applications has been proven. Architectural requirements and component design constraints have been determined. It is shown that the hardware overhead required for performing the relocation procedure is negligible compared to the total amount of FPGA resources. In addition, the component relocation time has been measured according to slot size. It is two orders of magnitude less than the reconfiguration time for the entire target FPGA, which allows quite rapid mode switching or circuit restoration.
Starting Page	909
Ending Page	914
File Size	1160927
Page Count	6
File Format	PDF
ISBN	9781424453344
DOI	10.1109/CSE.2009.493
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-29
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	field programmable gate arrays system design Size measurement Time measurement Circuit faults Resource virtualization video processing Runtime embedded systems Cost function Hardware dynamic reconfiguration Resource management System-on-a-chip Field programmable gate arrays
Content Type	Text
Resource Type	Article

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