NDLI: FPGA implementation of an efficient multiplier over finite fields GF(2/sup m/)

Content Provider	IEEE Xplore Digital Library
Author	Garcia-Martinez, M.A. Posada-Gomez, R. Morales-Luna, G. Rodriguez-Henriquez, F.
Copyright Year	2005
Description	Author affiliation: Instituto Tecnologico de Orizaba (Garcia-Martinez, M.A.; Posada-Gomez, R.)
Abstract	Arithmetic operations over finite fields $GF(2^{m})$ are widely used in cryptography, error-correcting codes and signal processing. In particular, multiplication is especially relevant since other arithmetic operators, such as division or exponentiation, which they usually utilize multipliers as building blocks. Hardware implementation of field multiplication may provide a great speedup in procedure's performance, which easily exceeds the one observed in software platforms. In this paper we deal with an FPGA implementation of an efficient serial multiplier over the binary extension fields $GF(2^{193})$ and $GF(2^{239}).$ Those extension fields are included among the ones recommended by NIST (National Institute of Standards and Technology) standards for Elliptic Curve Cryptography. Our multiplier is of type Serial/Parallel LSB-first and operates with a latency of m-clock cycles, where m is the length of the field word. We calculate the space complexity attending the number of slices used in the FPGA
Starting Page	5
Ending Page	26
File Size	131190
Page Count	22
File Format	PDF
ISBN	0769524567
DOI	10.1109/RECONFIG.2005.18
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-09-28
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Software performance NIST Signal processing Elliptic curve cryptography Hardware Error correction codes Galois fields Field programmable gate arrays Delay Arithmetic
Content Type	Text
Resource Type	Article

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