NDLI: 3D Monte Carlo study of scaled SOI FinFETs using 2D Schrödinger quantum corrections

Content Provider	IEEE Xplore Digital Library
Author	Elmessary, M.A. Nagy, D. Aldegunde, M. Lindberg, J. Dettmer, W.G. Peric, D. Garcia-Loureiro, A.J. Martinez, A. Kalna, K.
Copyright Year	2014
Description	Author affiliation: ESDC, Swansea Univ., Swansea, UK (Elmessary, M.A.; Nagy, D.; Aldegunde, M.; Martinez, A.; Kalna, K.) \|\| H.H. Wills Phys. Lab., Univ. of Bristol, Bristol, UK (Lindberg, J.) \|\| C2EC, Swansea Univ., Swansea, UK (Dettmer, W.G.; Peric, D.) \|\| CITIUS, Univ. de Santiago de Compostela, Santiago de Compostela, Spain (Garcia-Loureiro, A.J.)
Abstract	SOI Si FinFETs scaled to gate lengths of 12.8 nm, 10.7 nm and 8.1 nm are simulated using 3D Finite Element Monte Carlo simulations with 2D Schrödinger based quantum corrections considering two cross-sections: rectangular and triangular, with rounded corners, in the preferred (110) channel orientation. The rectangular FinFETs give larger drive currents per perimeter than the triangular FinFETs but are outperformed by the triangular ones when normalised by channel area. In the scaling process, the drive current increases by about 5% (4%) and 5% (1%) for rectangular (triangular) cross-sections with nearly ideal sub-thresholds of 72 (66) mV/dec. The effect of interface roughness increases during the scaling from 3% to 12% and affects stronger the triangular cross-section FinFETs.
Starting Page	97
Ending Page	100
File Size	645834
Page Count	4
File Format	PDF
ISBN	9781479937189
DOI	10.1109/ULIS.2014.6813925
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-04-07
Publisher Place	Sweden
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Solid modeling Three-dimensional displays Monte Carlo methods Monte Carlo Schro¨dinger equation FinFET Logic gates FinFETs Silicon Mathematical model Finite Elements
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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