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Content Provider | IEEE Xplore Digital Library |
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Author | Yongqing Ren Hong An Ming Cong Guang Xu Li Wang |
Copyright Year | 2009 |
Abstract | The trend in wire delays due to resistance is becoming a significant problem for microprocessor designers, forcing radically new tiled microprocessor architecture designs. This type of architecture will necessarily incorporate on-chip networks topology. This paper examines a few of the possible on-chip network topology in the context of tiled processor architectures. Firstly, by investigating some proposed tiled processor architecture, we observe that the on chip network interconnecting is the critical design point in the architectures. After that, we discuss the candidate topologies of on-chip network topology that satisfy these properties. Finally, a detailed experimental evaluation of these networks topology is presented to highlight the scalability and performance of these tiled processor architectures. Results show that we can achieve performance improvement by modifying basic mesh appropriately according to the granularity of the tile within technology restrictions. |
Starting Page | 77 |
Ending Page | 81 |
File Size | 452226 |
Page Count | 5 |
File Format | |
ISBN | 9780769536057 |
DOI | 10.1109/CSO.2009.233 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2009-04-24 |
Publisher Place | China |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Process design Network topology Tiles Microprocessors Network-on-a-chip Switches Computer architecture Registers Wire Delay |
Content Type | Text |
Resource Type | Article |
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