NDLI: Real-Time power management for a multi-performance processor

Content Provider	IEEE Xplore Digital Library
Author	Ishihara, T.
Copyright Year	2009
Description	Author affiliation: System LSI Research Center, Kyushu University, JAPAN (Ishihara, T.)
Abstract	This paper presents an energy efficient embedded processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded real-time system design. The processor consists of multiple same-ISA PE (processing element) cores and a selective set-associative cache memory. The PE-cores differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating. The major advantage over the DVS processors is a small overhead for changing its performance. Our processor can change its performance within 1.5 microsecond and dissipates about 10 nano-joule while conventional DVS processors need hundreds of microseconds and dissipate a few micro-joule for each voltage transition. Our processor makes it possible to use the DVS control in embedded real-time systems and to perform more sophisticated dynamic power management.
Starting Page	147
Ending Page	152
File Size	145224
Page Count	6
File Format	PDF
ISBN	9781424450343
DOI	10.1109/SOCDC.2009.5423892
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-22
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Real time systems Energy consumption Power system management Cache memory Control systems Dynamic voltage scaling Voltage control Embedded systems Energy efficiency Real-time systems Microprocessor Low-power design Energy management Clocks
Content Type	Text
Resource Type	Article

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