NDLI: A novel low power and high speed Wallace tree multiplier for RISC processor

Content Provider	IEEE Xplore Digital Library
Author	Vinoth, C. Bhaaskaran, V.S.K. Brindha, B. Sakthikumaran, S. Kavinilavu, V. Bhaskar, B. Kanagasabapathy, M. Sharath, B.
Copyright Year	2011
Description	Author affiliation: SSN College of Engineering, Kalavakkam, Rajiv Gandhi Salai, (Off) Chennai, Tamil Nadu, India (Vinoth, C.; Bhaaskaran, V.S.K.; Brindha, B.; Sakthikumaran, S.; Kavinilavu, V.; Bhaskar, B.; Kanagasabapathy, M.; Sharath, B.)
Abstract	Power dissipation of integrated circuits is a major concern for VLSI circuit designers. A Wallace tree multiplier is an improved version of tree based multiplier architecture. It uses carry save addition algorithm to reduce the latency. This paper aims at additional reduction of latency and power consumption of the Wallace tree multiplier. This is accomplished by the use of 4:2, 5:2 compressors and by the use of Sklansky adder. The result shows that the proposed architecture is 44.4% faster than the conventional CMOS architecture, along with 11% of reduced power consumption realization at 200MHz. The simulations have been carried out using the TANNER EDA tool employing the 350nm CMOS technology library file from Austria Micro System.
Starting Page	330
Ending Page	334
File Size	329825
Page Count	5
File Format	PDF
ISBN	9781424486786
e-ISBN	9781424486793
DOI	10.1109/ICECTECH.2011.5941617
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-08
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand multiplier Very large scale integration Compressors Wallace tree adder Sklansky adder Delay compressors Computer architecture CMOS integrated circuits Adders low power VLSI
Content Type	Text
Resource Type	Article

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