NDLI: Implementation of an accurate Farsi Handwritten digit recognition system on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Moradi, M. Poormina, M.A. Razzazi, F.
Copyright Year	2009
Description	Author affiliation: Electrical Engineering Department, Science & Research Branch of Islamic Azad University, Tehran, Iran (Moradi, M.; Poormina, M.A.; Razzazi, F.)
Abstract	An accurate Farsi Handwritten digit recognition system based on FPGA (Field Programmable Gate Arrays) implementation is proposed in this paper. For obtain high accuracy, we used a combined method for feature extraction. This method of feature extraction is appropriate for FPGA implementation as it can be implemented only with add and subtract operations. This greatly speeds up the process. This method is used to extract the features from normalized 40*40 pixel handwritten digit images. Applying this method to a Farsi digit recognition system is implemented using a two-layer MLP (Multi Layer Perceptron) artificial neural network with few neurons in the hidden layer. The system is simple, less complex and more accurate than the other similar systems.
Starting Page	401
Ending Page	404
File Size	4247726
Page Count	4
File Format	PDF
ISBN	9781424446063
DOI	10.1109/PACIIA.2009.5406572
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-28
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FPGA Artificial neural networks Pattern recognition Optical character recognition software MLP neural network Handwriting recognition Neural networks Multilayer perceptrons Farsi Handwritten Digit Recognition Feature extraction Hardware elastic meshing Field programmable gate arrays Computational intelligence statistical approach
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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