NDLI: Optimal transistor sizing and voltage scaling for minimal energy use at fixed performance

Content Provider	IEEE Xplore Digital Library
Author	Oklobdzija, V.G. Aktan, M. Baran, D.
Copyright Year	2012
Description	Author affiliation: National Research Institute of Electronics and Cryptology, Gebze, Turkey (Baran, D.) \|\| New Mexico State University, NM 88003 USA (Oklobdzija, V.G.; Aktan, M.)
Abstract	This paper presents a simple sizing method for low-power that is comparable in speed and simplicity to the Logical Effort sizing. Yet, the accuracy of the results is in the range of simulation errors. The method is two orders of magnitude faster than methods based on convex optimization, allowing to make quick design choices and architectural trade-offs. In the standard cell environment the method can reduce power by more than 30% over existing designs obtained using synthesis tools. These results are confirmed on examples implemented in 45nm process.
Starting Page	1
Ending Page	10
File Size	661401
Page Count	10
File Format	PDF
ISBN	9781467326964
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-09
Publisher Place	Argentina
Access Restriction	Subscribed
Rights Holder	EDIUNS
Subject Keyword	Transistor Sizing Integrated Circuits Synthesis Digital Integrated Circuits Digital Circuit Optimization Delay Optimization Very Large Scale of Integration Design Methodology Low Power Design Integrated Circuits Modeling Logic gates Capacitance Convex functions Transistors Integrated circuit modeling
Content Type	Text
Resource Type	Article

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Optimal transistor sizing and voltage scaling for minimal energy use at fixed performance