NDLI: FPGA design of a variable sampling period PLL with a Digital Notch Filter for distorted grids

Content Provider	IEEE Xplore Digital Library
Author	Carugati, I. Orallo, C. Donato, P.G. Maestri, S.
Copyright Year	2011
Description	Author affiliation: Laboratorio de Instrumentación y Control, Universidad Nacional de Mar del Plata, CONICET (Carugati, I.; Orallo, C.; Donato, P.G.; Maestri, S.)
Abstract	This paper describes the implementation of a novel three-phase PLL for distorted grids in a Field Programmable Gate Array (FPGA). It is based on the concept of a variable sampling period, which allows to automatically adjust the sampling frequency to be an integer multiple of the line frequency and a Digital Notch Filter (DNF), which is used in the loop to reject disturbances, such as unbalanced voltage and harmonics. Structural simplicity, robustness and harmonics rejection are some of the attractive features offered by the proposed system.
Starting Page	1
Ending Page	7
File Size	575397
Page Count	7
File Format	PDF
ISBN	9781457712364
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-08-11
Publisher Place	Argentina
Access Restriction	Subscribed
Rights Holder	EDIUNS
Subject Keyword	Field Programmable Gate Array (FPGA) Phase synchronization Harmonic analysis Time frequency analysis Synchronization Phase locked loops (PLL) Phase locked loops Digital filters Field programmable gate arrays Power harmonic filters
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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FPGA design of a variable sampling period PLL with a Digital Notch Filter for distorted grids