NDLI: Design and evaluation of a reconfigurable digital architecture for self-organizing maps

Content Provider	IEEE Xplore Digital Library
Author	Pino, B. Pelayo, F.J. Ortega, J. Prieto, A.
Copyright Year	1999
Description	Author affiliation: Dept. Arquitectura y Tecnologia de Computadores, Granada Univ., Spain (Pino, B.)
Abstract	A digital SIMD architecture to implement Self-Organizing Maps is presented. Custom bit-serial processing elements have been designed not only to obtain a high integration density (an area of 0.06 mm/sup 2/ per PE is estimated for a 0.25 /spl mu/m process and a standard cell design) but also to improve flexibility. The dimensionality of the map, the topological neighbourhood and the kernel function shape are programmable. A modular approach allows several neurochips to be interconnected to expand both the number of neurons and the number of synapses per neuron, performing a mixed synapse/neuron parallelism. In a system composed of a fixed number of neurochips, the number of neurons and synapses physically implemented can be reconfigured in order to achieve the optimal exploitation of hardware resources. The performance of the proposed architecture for fully implemented networks and virtual nets has been evaluated. A significant speedup improvement is achieved in comparison with a similar architecture without synapse parallelism.
Starting Page	395
Ending Page	402
File Size	952058
Page Count	8
File Format	PDF
ISBN	0769500439
DOI	10.1109/MN.1999.758892
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-04-09
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Concurrent computing Self organizing feature maps Neurons Neural networks Signal processing algorithms Computer architecture Artificial neural networks Parallel processing Hardware Hip
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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