NDLI: VLSI implementation of a modular and programmable neural architecture

Content Provider	IEEE Xplore Digital Library
Author	Cardarilli, G.C. D'Alessandro, C. Marinucci, P. Bordoni, F.
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. Eng., L'Aquila Univ., Italy (Cardarilli, G.C.)
Abstract	A mixed-signal VLSI chip architecture for multi-layer feedforward neural network implementation with digitally programmable synapses is presented. The chip realizes a fully connected single-layer network, configurable as a 48 input/48 output neurons with 2304 5-bit synapses or as a 24 input/24 output neurons with 1152 9-bit synapses. This single layer network can be reconfigured as a multi-layer network. Another important chip feature is the possibility of connecting the chips in order to obtain a more complex multi-layer neural network. The core of the authors' architecture is a very efficient circuit block, "distributed sigmoid-synapse", that they used to implement each of the 2304 5-bit synapses included in the programmable neural network. A prototyping chip, including all the basic block of neural architecture, is now processed by ES2 with 1.0 /spl mu/m CMOS technology. Finally, the authors report the architecture of a possible system for the evaluation of the VLSI chip performances. Parameter mismatches present in the chip were considered to be not critical because it is possible to account them during the training of the neural network by using a special chip-in-the-loop training algorithm. The authors planned to use this chip in pattern recognition and image processing applications.
Starting Page	218
Ending Page	225
File Size	601863
Page Count	8
File Format	PDF
ISBN	0818667109
DOI	10.1109/ICMNN.1994.593713
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-09-26
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Neural networks Neurons Circuits Prototypes Very large scale integration CMOS technology CMOS process Feedforward neural networks Joining processes Multi-layer neural network
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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