NDLI: The Wave Pipeline Effect on LUT-Based FPGA Architectures

Content Provider	IEEE Xplore Digital Library
Author	Boemo, E.I. Lopez-Buedo, S. Meneses, J.M.
Copyright Year	1996
Description	Author affiliation: Ciudad Universitaria, Madrid - España (Boemo, E.I.)
Abstract	The wave pipeline effect is based on the equalization of all path delays in order to allow several "waves" of data to travel along the circuit with a separation several times smaller than the maximum combinational delay of the circuit. The construction of wave pipelines requires gates and buffers with data-independent delay, and a well-characterized interconnection network delay model, in order to allow the equalization process to be managed by the designer. These features are inherently present in several RAM-based FPGAs architectures. Look-up tables (LUTs) permit the delay of digital blocks with different types of gates or different logic depth to be equalized; moreover, the delay of a FPGA interconnection network is completely parameterized and is a priori known. This paper describes a LUT-based wave pipeline array multiplier manually implemented using a Xilinx chip. The results show that, even for a single-phase non-skewed clocking strategy, a throughput as high as 85 MHz (measured) can be achieved, with 8 waves running in a 13-LUT logic depth combinational array with registered I/O, producing an initial latency of 9 clock cycles. For the FPGA architecture and the topology selected, such a large throughput/latency ratio would be impossible using classical pipelininig.
Starting Page	45
Ending Page	50
File Size	361615
Page Count	6
File Format	PDF
ISBN	0769525768
DOI	10.1109/FPGA.1996.242342
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-02-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Delay effects Multiprocessor interconnection networks Pipelines Circuits Throughput Table lookup Field programmable gate arrays Logic arrays Propagation delay Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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